Renesas MN4 Spécifications télécharger pdf (Page 7)

V850E2/MN4 CSIH Control

R01AN0924EJ0100 Rev.1.00 Page 7 of 40

Feb 10, 2012

1.4 Main Loop Processing

• The operation of data transfer via the CSIH depends on the memory mode.

In dual buffer mode, the transmitting CSIH0 transmits nine bytes of data and the receiving CSIH3 receives the nine

bytes of data from the CSIH0. The internal RAM has nine bytes (one byte (one block data) × nine) of an area for

each of the user transmit array to store transmit data and the user receive array to store receive data.

In direct access mode, the transmitting CSIH0 prepares six-byte data, divides the data into three bytes as a job, and

transmits the two jobs. The receiving CSIH3 receives six bytes of data and stores the data in the internal RAM. The

internal RAM has the six-byte (one byte (one block data) × six) user transmit array to store transmit data and the six-

byte user receive array to store receive data.

• The conditions under which data transfer via the CSIH starts depend on the memory mode.

<1> Transmission in CSIH master mode:

In direct access mode, data transmission is started by writing data to the CSIHnTX0W register after the setup

of the CSIH ends.

In dual buffer mode, data transmission is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1.

<2> Reception in CSIH slave mode:

In direct access mode, data reception is started by detecting external clock CSIHnTSCK.

In dual buffer mode, data reception is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1.

• Interrupts occur at the timings described below.

In direct access transmit mode, a transmit status interrupt (CSIHnTIC) occurs after each unit of data is transmitted.

In job mode, a job completion interrupt (CSIHnTIJC) occurs after the transfer of the job that is enabled by setting

the CSIH0CTL0.JOBE bit to 1 is completed.

In direct access receive mode, a receive status interrupt (CSIHnTIR) occurs each time data is received.

In dual buffer mode, a transmit status interrupt (CSIHnTIC) and a receive status interrupt (CSIHnTIR) occur after

the specified amount of data is transferred.

A communication status interrupt (CSIHnTIRE) is generated whenever a communication error occurs.

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Renesas MN4 Spécifications Page 7