MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
47
Flash mode selection bit
0 : Color signal of character
background part does not
flash
1 : Color signal of character
background part flashes
7
OSD control register
(OC : address 00CE
16
)
OSD control bit (Note 1)
0 : All-blocks display off
1 : All-blocks display on
Scan mode selection bit
0 : Normal scan mode
1 : Bi-scan mode
Border type selection bit
0 : All bordered
1 : Shadow bordered (Note 2)
Automatic solid space control
bit
0 : OFF
1 : ON
Window control bit
0 : OFF
1 : ON
Layer mixing control bits (Note 3)
b7 b6
0 0 : Logical sum (OR) of
layer 1’s color and
layer 2’s color
0 1 : Layer 1’s color has priority
1 0 : Layer 2’s color has priority
1 1 : Do not set
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V
SYNC
.
2 : Shadow border is output at right and bottom side of the font.
3 : Set “00” during displaying extra fonts.
Display layer
Layer 1
Layer 2
Dot size
1T
C ✕ 1/2H
1TC ✕ 1H
2TC ✕ 2H
3TC ✕ 3H
1TC ✕ 1/2H
1T
C ✕ 1H
2TC ✕ 2H
3TC ✕ 3H
1TC ✕ 1/2H
1TC ✕ 1H
2TC ✕ 2H
3TC ✕ 3H
1TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1/2H
1T
C ✕ 1H
1.5TC ✕ 1/2H
1.5TC ✕ 1H
b3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
b4
0
0
1
1
0
0
1
1
0
0
1
1
—
—
0
0
1
1
b6
0
0
1
1
1
Table 11. Setting value of block control registers
Pre-divide
ratio
✕ 1
✕ 2
✕ 3
✕ 1
✕ 2
b5
0
1
0
1
1
CS6
—
—
—
0
1
Notes 1: CS6 : Bit 6 of clock control register (Address 021616)
2: TC : OSD clock cycle divided in the pre-divide circuit
3: H:HSYNC
7
Block control register i
(i = 1 to 16)
(BCi : addresses 00D0
16
to 00DF)
Display mode selection bits
b1 b0
0 0 : Display OFF
0 1 : OSD mode
1 0 : CC mode
1 1 : EXOSD mode
Border control bit
0 : Border OFF
1 : Border ON
Notes : Bit 4 of the color code 1 controls OUT1 output
when bit 7 is “0.”
Bit 4 of the color code 1 controls OUT2 output
when bit 7 is “1.”
Dot size selection bit
Refer to Table 11.
Pre-divide ratio
•
layer selection
bits
Refer to Table 11.
OUT 2 output control bit (Note)
0 : OUT2 output OFF
1 : OUT2 output ON
Fig. 50. Structure of block control registers
Fig. 49. Structure of OSD control register
0
0
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