Renesas Asynchronous SH7145F Manuel d'utilisateur télécharger pdf (Page 2)

SH7145 Group

SCI Break Detection

REJ06B0384-0100Z/Rev.1.00 September 2004 Page 2 of 20

1. Specifications

As shown in figure 1, break detection is performed using channel 0 (ch0) of the SH7145F's SCI. Break detection is only

possible in asynchronous communication. In the SH7145, break detection is not performed by hardware, and so is

executed by software.

Break detection is performed by monitoring the level of the RxD pin when a framing error occurs: if the RxD pin is at

low level, it is regarded that a break has occurred. In this sample task, break detection is performed after receiving three

bytes of data. Confirmation of the RxD pin level at the time of a framing error is performed three times at 5 msec

intervals, and a break is detected if the level is low all three times. When a break is detected, the RE bit of SCR_0 is

cleared to 0 to terminate the reception by the SCI. The RxD pin state is checked using a compare-match timer interrupt.

The SCI communication format is 19,200 bps, 8 bits, one stop bit, and no parity.

SCI

(ch0)

On-chip RAM

3.3 V

1 byte

SH7145

MCU to

communicate

by SCI

RxD

TxD

3.3 V

Figure 1 SH7145 SCI Reception Connection Diagram

Table 1 Asynchronous Serial Reception Format

Item Setting

Bit rate 19200 bps

Data length 8 bits

Parity bit none

Stop bit 1 bit

Serial/parallel conversion format LSB first

1 2 3 4 5 6 7 ... 19 20

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Renesas Asynchronous SH7145F Manuel d'utilisateur Page 2