Renesas Emulation Pod M306H2T-RPD-E Informations techniques télécharger pdf (Page 49)

M306H5T3-RPD-E User’s Manual 4. Specifications

REJ10J0866-0100Z Rev.1.00 Dec.16, 2004

Page 47 of 66

Vcc=5V

4.2.3 Timing Requirements

Table 4.4 and Figure 4.3 show the timing requirements.

Table 4.4 Timing requirements

Actual MCU [ns] This product [ns]

Symbol Item

Min. Max. Min. Max.

tsu(DB-RD) Data input setup time 40 65

tsu(RDY-BCLK) RDY* input setup time 30 55

tsu(HOLD-BCLK) HOLD* input setup time 40 80

th(RD-DB) Data input hold time 0 See left

th(BCLK-RDY) RDY* input hold time 0 See left

th(BCLK-HOLD) HOLD* input hold time 0 See left

td(BCLK-HLDA) HLDA* output delay time 40 See left

Figure 4.3 Timing requirements

Common to with wait and no-wait (actual MCU)

Hi-Z

* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.

BCLK

HOLDInput

HLDAOutput

P0,P1,P2,P3,P4,

0 --P52

tsu(HOLD-BCLK)

td(BCLK-HLDA)

th(BCLK-HOLD)

Hi-Z

BCLK

HOLD

Input

HLDAOutput

P0,P1,P2,P3,P4,

0--P52

tsu(HOLD-BCLK)

td(BCLK-HLDA)

th(BCLK-HOLD)

td(BCLK-HLDA)

Common to with wait and no-wait (this product)

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 67 68

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Renesas Emulation Pod M306H2T-RPD-E Informations techniques Page 49