Renesas M16C/6V Informations techniques télécharger pdf (Page 70)

M306V8T-EPB User’s Manual 4. Hardware Specifications

REJ10J0777-0100 Rev.1.00 2005.08.01 Page 68 of 90

Figure 4.2 Memory expansion mode and microprocessor mode (2-wait, accessing external area, using multiplex bus)

Read timing

Write timing

BCLK

CSi

ADi

BHE

ALE

ADi

/DBi

td(BCLK-CS)

th(BCLK-CS)

tcyc

td(BCLK-AD)

th(BCLK-AD)

th(RD-CS)

td(BCLK-ALE)

th(BCLK-ALE)

th(RD-AD)

td(BCLK-RD)

th(BCLK-RD)

tac3(RD-DB)

Hi-Z

tsu(DB-RD)

th(RD-DB)

BCLK

CSi

ADi

BHE

ALE

WR,

WRL,WRH

ADi

/DBi

td(BCLK-CS)

th(BCLK-CS)

tcyc

td(BCLK-AD)

td(BCLK-ALE)

th(BCLK-ALE)

th(WR-AD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

td(DB-WR)

th(BCLK-AD)

th(WR-CS)

th(WR-DB)

th(BCLK-DB)

td(AD-ALE) th(ALE-AD)

td(AD-RD)

tdz(RD-AD)

td(AD-ALE) th(ALE-AD)

td(AD-WR)

1 2 ... 65 66 67 68 69 70 71 72 73 74 75 ... 91 92

To our customers 1
M306V8T-EPB 3
Preface 5
Important 6
WARNING 8
CAUTION 8
WARNING 9
CAUTION 10
Contents 11
User Registration 13
Terminology 14
1. Outline 15
1.3 System Configuration 17
System status 18
Target status 18
IMPORTANT 19
1.4 Specifications 20
1.5 Operating Environment 21
2. Setup 22
2.8 Self-check 30
2.10 Switch Settings 34
●EPB TRGT 36
J1-4：GND 43
J1-3：Oscillator output 43
J1-2：GND 43
J1-1：VCC 43
INTERNAL 52
3.2 Editor (Source) Window 54
3.4 Trace Window 62
3.5 RAM Monitor Window 65
4. Hardware Specifications 66
4.2 Access Timing 67
Write timing 68
4.4 Connection Diagrams 75
4.5 External Dimensions 77
5. Troubleshooting 84
6. Maintenance and Guarantee 89
User’s Manual 92

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