Renesas R8C/17 Informations techniques télécharger pdf (Page 14)

R8C/16 Group, R8C/17 Group 2. Central Processing Unit (CPU)

Rev.2.00 Jan 30, 2006 Page 12 of 35

REJ03B0101-0200

2.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt.

An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The

I flag is set to “0” when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.

The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of

software interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

When write to this bit, set to “0”. When read, its content is indeterminate.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 39 40

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Renesas R8C/17 Informations techniques Page 14