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Renesas Renasas Single-Chip Microcomputer SH7086 manuels

Manuels d'utilisation et guides de l'utilisateur pour Mise en réseau Renesas Renasas Single-Chip Microcomputer SH7086.
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Renesas Renasas Single-Chip Microcomputer SH7086 Informations techniques (108 pages)


marque: Renesas | Catégorie: Mise en réseau | Taille: 5.58 MB |

 

Table des matières

To our customers

1

Table of Contents

4

1. SH7086

5

2.1 Main Facilities

7

Flash Development Toolkit

10

3.5 User Boot Mode

53

3.6 User Program Mode

69

Files for User Program Mode

82

5.1 Source File List

82

5.2 Module List

83

5.4 Program Flow

87

6.1 Header Files

90

6.3 RAM Main Process

95

7. Programming Guide

101

7.3 Using the Libraries

103

7.5 Module Specifications

105

Revision Record

107

Renesas Renasas Single-Chip Microcomputer SH7086 Manuel d'utilisateur (21 pages)


marque: Renesas | Catégorie: Mise en réseau | Taille: 0.13 MB |

 

Table des matières

To our customers

1

1. Specification

4

2. Applicable Conditions

5

4. Principles of Operation

9

SH7080 Group

10

5.4 Register Settings

13

6. Flowchart

17

6.1 Main Routine

17

6.2 A/D Conversion Routine

18

Website and Support

20

Revision Record

20

Renesas Renasas Single-Chip Microcomputer SH7086 Manuel d'utilisateur (308 pages)


marque: Renesas | Catégorie: Mise en réseau | Taille: 1.13 MB |

 

Table des matières

To our customers

1

M16C/60, M16C/20, M16C/Tiny

3

Using This Manual

5

M16C Family Documents

6

Table of Contents

7

Quick Reference-1

9

Quick Reference-2

10

Quick Reference-3

11

Quick Reference by Function

11

Quick Reference-4

12

Quick Reference-5

13

Quick Reference-6

14

Quick Reference-7

15

Quick Reference-8

16

Quick Reference-9

17

Quick Reference-10

18

Chapter 1

19

Overview

19

Chapter 1 Overview

20

1.1.2 Speed performance

20

1.2 Address Space

21

1.3 Register Configuration

22

1.4 Flag Register (FLG)

24

1.4.11 Bit 15: Reserved area

25

1.5 Register Bank

26

1.7 Data Types

28

1.7.2 Decimal

29

1.7.3 Bits

30

1.7.4 String

33

1.8 Data Arrangement

34

1.9 Instruction Format

36

1.10 Vector Table

37

1.10.2 Variable Vector Table

38

Chapter 2

39

Addressing Modes

39

2.1 Addressing Modes

40

2.2 Guide to This Chapter

41

Chapter 2 Addressing Modes

42

Chapter 3

51

Functions

51

3.1 Guide to This Chapter

52

(3) Syntax

53

Unconditional jump

56

Absolute value

57

Add with carry

58

ADCF ADCF

59

Add without carry

60

ADJNZ ADJNZ

62

Logically AND

63

BAND BAND

65

Clear bit

66

Bit Move Condition

67

Logically AND inverted bits

68

BNOR BNOR

69

BNOTBNOT

70

BNTST BNTST

71

Exclusive OR inverted bits

72

Logically OR bits

73

Debug interrupt

74

BSET BSET

75

BTST BTST

76

BTSTC BTSTC

77

BTSTS BTSTS

78

Exclusive OR bits

79

Compare

80

DADC DADC

82

DADD DADD

83

Decrement

84

Signed divide

85

DIVU DIVU

86

DIVX DIVX

87

DSBB DSBB

88

DSUB DSUB

89

ENTER ENTER

90

EXITD EXITD

91

EXTS EXTS

92

Clear flag register bit

93

FSET FSET

94

Increment

95

Interrupt by INT instruction

96

INTO INTO

97

Jump on condition

98

Unconditional jump

99

JMPI JMPI

100

JMPS JMPS

101

Subroutine call

102

Indirect subroutine call

103

JSRS JSRS

104

Transfer to control register

105

LDCTX LDCTX

106

Chapter 3 Functions

107

LoaD from EXtra far data area

107

LDINTB LDINTB

108

LDIPL LDIPL

109

Transfer

110

Chapter 3 Functions

111

MOVA MOVA

112

Transfer 4-bit data

113

Signed multiply

114

MULU MULU

115

Two’s complement

116

No operation

117

Invert all bits

118

________

118

Logically OR

119

Restore register/memory

121

POPC POPC

122

POPM POPM

123

PUSH PUSH

124

PUSHA PUSHA

125

PUSHC PUSHC

126

PUSHM PUSHM

127

REIT REIT

128

RMPA RMPA

129

ROLC ROLC

130

RORC RORC

131

Return from subroutine

133

Subtract with borrow

134

SBJNZ SBJNZ

135

Shift arithmetic

136

Shift logical

137

SMOVB SMOVB

138

SMOVF SMOVF

139

SSTR SSTR

140

STore from Control register

141

STCTX STCTX

142

STore to EXtra far data area

143

STNZ STNZ

144

Conditional transfer

145

STZX STZX

146

Subtract without borrow

147

UNDefined instruction

150

WAIT WAIT

151

XCHG XCHG

152

Exclusive OR

153

Chapter 4

155

4.1 Guide to This Chapter

156

Chapter 4 Instruction Code

157

(1) Mnemonic

157

(2) Syntax

157

(3) Instruction code

157

(4) Table of cycles

157

(1) ABS.size dest

158

(1) ADC.size #IMM, dest

158

(2) ADC.size src, dest

159

(1) ADCF.size dest

160

(1) ADD.size:G #IMM, dest

160

(2) ADD.size:Q #IMM, dest

161

(3) ADD.B:S #IMM8, dest

162

(4) ADD.size:G src, dest

163

(6) ADD.size:G #IMM, SP

164

(5) ADD.B:S src, R0L/R0H

164

(7) ADD.size:Q #IMM, SP

165

(1) AND.size:G #IMM, dest

167

(2) AND.B:S #IMM8, dest

167

(3) AND.size:G src, dest

168

(4) AND.B:S src, R0L/R0H

169

(1) BAND src

170

(1) BCLR:G dest

170

(2) BCLR:S bit, base:11[SB]

171

(1) BNAND src

173

(1) BNOR src

174

(1) BNOT:G dest

174

(2) BNOT:S bit, base:11[SB]

175

(1) BNTST src

175

(1) BNXOR src

176

(1) BOR src

176

(1) BSET:G dest

177

(2) BSET:S bit, base:11[SB]

178

(1) BTST:G src

178

(2) BTST:S bit, base:11[SB]

179

(1) BTSTC dest

179

(1) BTSTS dest

180

(1) BXOR src

180

(1) CMP.size:G #IMM, dest

181

(2) CMP.size:Q #IMM, dest

182

(3) CMP.B:S #IMM8, dest

183

(4) CMP.size:G src, dest

184

(5) CMP.B:S src, R0L/R0H

185

(1) DADC.B #IMM8, R0L

185

(2) DADC.W #IMM16, R0

186

(3) DADC.B R0H, R0L

186

(4) DADC.W R1, R0

187

(1) DADD.B #IMM8, R0L

187

(2) DADD.W #IMM16, R0

188

(3) DADD.B R0H, R0L

188

(4) DADD.W R1, R0

189

(1) DEC.B dest

189

(2) DEC.W dest

190

(1) DIV.size #IMM

190

(2) DIV.size src

191

(1) DIVU.size #IMM

191

(2) DIVU.size src

192

(1) DIVX.size #IMM

192

(2) DIVX.size src

193

(1) DSBB.B #IMM8, R0L

193

(2) DSBB.W #IMM16, R0

194

(3) DSBB.B R0H, R0L

194

(4) DSBB.W R1, R0

195

(1) DSUB.B #IMM8, R0L

195

(2) DSUB.W #IMM16, R0

196

(3) DSUB.B R0H, R0L

196

(4) DSUB.W R1, R0

197

(1) ENTER #IMM8

197

(1) EXITD

198

(1) EXTS.B dest

198

(2) EXTS.W R0

199

(1) FCLR dest

199

(1) FSET dest

200

(1) INC.B dest

200

(2) INC.W dest

201

(1) INT #IMM

201

(1) INTO

202

(1) JMP.S label

203

(2) JMP.B label

204

(3) JMP.W label

204

(1) JMPI.W src

205

(4) JMP.A label

205

(2) JMPI.A src

206

(1) JMPS #IMM8

206

(1) JSR.W label

207

(2) JSR.A label

207

(1) JSRI.W src

208

(2) JSRI.A src

208

(1) JSRS #IMM8

209

(1) LDC #IMM16, dest

209

(2) LDC src, dest

210

(1) LDCTX abs16, abs20

210

(1) LDE.size abs20, dest

211

(2) LDE.size dsp:20[A0], dest

211

(3) LDE.size [A1A0], dest

212

(1) LDINTB #IMM

212

(1) LDIPL #IMM

213

(1) MOV.size:G #IMM, dest

213

(2) MOV.size:Q #IMM, dest

214

(3) MOV.B:S #IMM8, dest

215

(4) MOV.size:S #IMM, dest

216

(5) MOV.B:Z #0, dest

216

(6) MOV.size:G src, dest

217

(7) MOV.B:S src, dest

218

(8) MOV.B:S R0L/R0H, dest

218

(9) MOV.B:S src, R0L/R0H

219

(1) MOVA src, dest

220

R0L, dest

221

(1) MUL.size #IMM, dest

223

(2) MUL.size src, dest

224

(1) MULU.size #IMM, dest

225

(2) MULU.size src, dest

226

(1) NEG.size dest

227

(2) NOT.B:S dest

228

(1) NOT.size:G dest

228

(1) OR.size:G #IMM, dest

229

(2) OR.B:S #IMM8, dest

229

(3) OR.size:G src, dest

230

(4) OR.B:S src, R0L/R0H

231

(1) POP.size:G dest

231

(2) POP.B:S dest

232

(3) POP.W:S dest

232

(1) POPC dest

233

(1) POPM dest

233

(1) PUSH.size:G #IMM

234

(2) PUSH.size:G src

234

(3) PUSH.B:S src

235

(4) PUSH.W:S src

235

(1 ) PUSHA src

236

(1) PUSHC src

236

(1) PUSHM src

237

(1) REIT

237

(1) RMPA.size

238

(1) ROLC.size dest

238

(1) RORC.size dest

239

(1) ROT.size #IMM, dest

240

(2) ROT.size R1H, dest

241

(1) SBB.size #IMM, dest

242

(2) SBB.size src, dest

243

(1) SHA.size #IMM, dest

245

(2) SHA.size R1H, dest

246

(3) SHA.L #IMM, dest

246

(4) SHA.L R1H, dest

247

(1) SHL.size #IMM, dest

248

(2) SHL.size R1H, dest

249

(3) SHL.L #IMM, dest

249

(4) SHL.L R1H, dest

250

(1) SMOVB.size

250

(1) SMOVF.size

251

(1) SSTR.size

251

(1) STC src, dest

252

(2) STC PC, dest

252

(1) STE.size src, abs20

253

(1) STCTX abs16, abs20

253

(2) STE.size src, dsp:20[A0]

254

(3) STE.size src, [A1A0]

254

(1) STNZ #IMM8, dest

255

(1) STZ #IMM8, dest

255

(1) STZX #IMM81, #IMM82, dest

256

(1) SUB.size:G #IMM, dest

256

(2) SUB.B:S #IMM8, dest

257

(3) SUB.size:G src, dest

258

(4) SUB.B:S src, R0L/R0H

259

(1) TST.size #IMM, dest

259

(2) TST.size src, dest

260

(1) WAIT

261

(1) XCHG.size src, dest

262

(1) XOR.size #IMM, dest

263

(2) XOR.size src, dest

264

Chapter 5

265

Interrupt

265

Chapter 5 Interrupt

267

5.1.2 Software Interrupts

267

____________

268

5.2 Interrupt Control

269

5.3 Interrupt Sequence

272

5.3.3 Saving Registers

274

5.5 Interrupt Priority

277

5.6 Multiple Interrupts

278

5.7.1 Reading address 0000016

280

5.7.2 Setting the SP

280

Chapter 6

283

Calculation Number of Cycles

283

Calculation number of cycles

285

Q & A

289

Q&A-2

290

Q&A-3

291

Q&A-4

292

Q&A-5

293

Q&A-6

294

Glossary

295

Glossary-2

296

Glossary-3

297

Glossary-4

298

Table of symbols

299

Symbol-2

300

REVISION HISTORY

303

Software Manual

308

Renesas Renasas Single-Chip Microcomputer SH7086 Manuel d'utilisateur (31 pages)


marque: Renesas | Catégorie: Mise en réseau | Taille: 0.55 MB |

 

Table des matières

User's Manual

1

Table of Contents

2

Chapter 1. Preface

3

Chapter 2. Purpose

4

Chapter 3. Power Supply

5

Chapter 4. Board Layout

6

4.2. Board Dimensions

7

Chapter 5. Block Diagram

8

Chapter 6. User Circuitry

9

6.5. LCD Module

10

6.6. Option Links

11

6.7.Oscillator Sources

15

6.8.Reset Circuit

15

Chapter 7.Modes

16

Chapter 9. Headers

18

9.2. Application Headers

22

10.1. Overview

26

10.2. Compiler Restrictions

26

10.3.Breakpoint Support

26

10.4.Memory Map

27




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