Renesas SH7709S Manuel d'utilisateur télécharger pdf (Page 8)

Rev. 1.0, 07/03, page 4 of 38

Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is

performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU

specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In little-

endian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to

address 4n.

2.1.2 Power-On Sequence (SH7709S/SH7729R/SH7706)

To use the synchronous DRAM, specify modes after power-on. To initialize the synchronous

DRAM correctly, first specify the bus state controller registers and then specify the synchronous

DRAM mode register. When specifying the synchronous DRAM mode register, the address

signal value is latched depending on the combination of RAS, CAS, and RD/WR signals. In this

case, the bus state controller functions as follows. To write a designated value X to the DRAM

mode register, write data to address H'FFFFD000 + X for area 2 of synchronous DRAM and write

data to H'FFFFE000 + X for area 3 of synchronous DRAM. At this time, data written at addresses

H'FFFFD000 + X and H'FFFFE000 + X is ignored and the DRAM mode register is written in byte

units.

To specify burst read/single write, CAS latency as 1 to 3, sequential as lap type, and burst length

as 1, write arbitrary data in byte units to the addresses listed below.

Area 2 Area 3

32-bit bus width CAS latency 1 H'FFFFD840 H'FFFFE840

CAS latency 2 H'FFFFD880 H'FFFFE880

CAS latency 3 H'FFFFD8C0 H'FFFFE8C0

Area 2 Area 3

16-bit bus width CAS latency 1 H'FFFFD420 H'FFFFE420

CAS latency 2 H'FFFFD440 H'FFFFE440

CAS latency 3 H'FFFFD460 H'FFFFE460

By writing data to address H'FFFFD000 + X or address H'FFFFE000 + X, the precharge all banks

command (PALL) is first issued at cycle TRp1, and a mode register write command is issued at

the following cycle TMw1. The address signals when a mode register write command is issued are

as follows.

32-bit bus width A15 to A9 0000100 (Burst read and single write)

A8 to A6 CAS latency

A5 0 (Burst type = sequential)

A4 to A2 000 (Burst length 1)

16-bit bus width A14 to A8 0000100 (Burst read and single write)

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 43 44

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Renesas SH7709S Manuel d'utilisateur Page 8