Renesas MN4 Manuel d'utilisateur

APPLICATION NOTE R01AN0922EJ0100 Rev.1.00 Page 1 of 54 Jan 13, 2012 V850E2/MN4 Timer Array Unit Control Introduction This application note expl

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 10 of 54 Jan 13, 2012 4.4 Register Setup This section explains how to set up

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 11 of 54 Jan 13, 2012 4.4.2 TAUAn Prescaler Registers • TAUAn prescaler clo

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 12 of 54 Jan 13, 2012 Figure 4.8 TAUAnTPS Register Format (2/4)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 13 of 54 Jan 13, 2012 Figure 4.9 TAUAnTPS Register Format (3/4)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 14 of 54 Jan 13, 2012 Figure 4.10 TAUAnTPS Register Format (4/4) Setting

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 15 of 54 Jan 13, 2012 4.4.3 TAUAn Control Registers • TAUAn channel data re

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 16 of 54 Jan 13, 2012 • TAUAn channel counter register (TAUAnCNTm) This regi

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 17 of 54 Jan 13, 2012 Figure 4.13 TAUAnCNTm Register Format (2/2)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 18 of 54 Jan 13, 2012 • TAUAn channel mode OS register (TAUAnCMORm) This reg

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 19 of 54 Jan 13, 2012 Figure 4.15 TAUAnCMORm Register Format (2/4)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 2 of 54 Jan 13, 2012 1. Overview This application note illustrates the usage

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 20 of 54 Jan 13, 2012 Figure 4.16 TAUAnCMORm Register Format (3/4)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 21 of 54 Jan 13, 2012 Figure 4.17 TAUAnCMORm Register Format (4/4)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 22 of 54 Jan 13, 2012 Setting examples TAUA1CMOR0 = 0x0801; /* CK0, mast

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 23 of 54 Jan 13, 2012 Figure 4.18 TAUAnTS Register Format Setting exampl

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 24 of 54 Jan 13, 2012 • TAUAn channel enable status register (TAUAnTE) This

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 25 of 54 Jan 13, 2012 • TAUAn channel stop trigger register (TAUAnTT) This r

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 26 of 54 Jan 13, 2012 4.4.4 TAUAn Output Registers • TAUAn channel output en

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 27 of 54 Jan 13, 2012 • TAUAn channel output mode register (TAUAnTOM) This r

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 28 of 54 Jan 13, 2012 • TAUAn channel output configuration register (TAUAnTO

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 29 of 54 Jan 13, 2012 • TAUAn channel dead time output enable register (TAUA

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 3 of 54 Jan 13, 2012 2. Usage Environment This section explains the circuit d

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 30 of 54 Jan 13, 2012 • TAUAn channel real-time output enable register (TAUA

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 31 of 54 Jan 13, 2012 4.4.5 TAUAn Channel Output Level Registers • TAUAn ch

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 32 of 54 Jan 13, 2012 4.4.6 TAUAn Simultaneous Rewrite Registers • TAUAn ch

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 33 of 54 Jan 13, 2012 • TAUAn channel reload data control channel select reg

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 34 of 54 Jan 13, 2012 • TAUAn channel reload data mode register (TAUAnRDM) T

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 35 of 54 Jan 13, 2012 4.4.7 TAUJn Prescaler Registers • TAUJn prescaler clo

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 36 of 54 Jan 13, 2012 Figure 4.31 TAUJnTPS Register Format (2/3)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 37 of 54 Jan 13, 2012 Figure 4.32 TAUJnTPS Register Format (3/3) Setting

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 38 of 54 Jan 13, 2012 4.4.8 TAUJn Control Registers • TAUJn channel data re

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 39 of 54 Jan 13, 2012 • TAUJn channel counter register (TAUJnCNTm) This regi

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 4 of 54 Jan 13, 2012 3. Software This section describes the file organization

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 40 of 54 Jan 13, 2012 Figure 4.35 TAUJnCNTm read values

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 41 of 54 Jan 13, 2012 • TAUJn channel mode OS register (TAUJnCMORm) This reg

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 42 of 54 Jan 13, 2012 Figure 4.37 TAUJnCMORm Register Format (2/3)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 43 of 54 Jan 13, 2012 Figure 4.38 TAUJnCMORm Register Format (3/3) Setti

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 44 of 54 Jan 13, 2012 • TAUJn channel mode user register (TAUJnCMURm) This r

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 45 of 54 Jan 13, 2012 • TAUJn channel status register (TAUJnCSRm) This regi

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 46 of 54 Jan 13, 2012 • TAUJn channel status clear register (TAUJnCSCm) This

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 47 of 54 Jan 13, 2012 • TAUJn channel start trigger register (TAUJnTS) This

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 48 of 54 Jan 13, 2012 • TAUJn channel enable status register (TAUJnTE) This

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 49 of 54 Jan 13, 2012 • TAUJn channel stop trigger register (TAUJnTT) This r

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 5 of 54 Jan 13, 2012 4. Sample Application This section explains how to set u

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 50 of 54 Jan 13, 2012 4.4.9 TAUJn Output Registers • TAUJn channel output e

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 51 of 54 Jan 13, 2012 4.4.10 TAUJn Channel Output Level Registers • TAUJn c

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 52 of 54 Jan 13, 2012 4.5 Function Specifications This section describes th

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 53 of 54 Jan 13, 2012 4.5.4 Timer Array Unit J Control (tauj_control.c) [Fun

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 54 of 54 Jan 13, 2012 Website and Support Renesas Electronics Website http:/

A-1 Revision Record Description Rev. Date Page Summary 1.00 Jan 13, 2012 — First edition issued

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed

Notice1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to chan

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 6 of 54 Jan 13, 2012 4.1.2 Interrupt Processing Flow The INTTUAJ0I0 interrup

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 7 of 54 Jan 13, 2012 4.2 Details of TAUA Setup In this sample program, the T

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 8 of 54 Jan 13, 2012 Slave channel: Positive logic (TAUAnTOL.TAUAnTOLm = 0)

V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Page 9 of 54 Jan 13, 2012 4.3 Details of TAUJ Setup In this sample program, the T