Renesas PCA4738L-64A Informations techniques Page 42
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Noté. / 5. Basé sur avis des utilisateurs
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3802 Group
39
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
140
200
30
30
30
40
30
30
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
t
c(S
CLK1
)/2–30
t
c(S
CLK2
)/2–160
t
c(S
CLK1
)/2–30
t
c(S
CLK2
)/2–160
–30
0
10
10
Typ. Max.
t
wH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t
d(S
CLK1
–T
X
D)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK1
–T
X
D)
t
v(S
CLK2
–S
OUT2
)
tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 36
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P5
1/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.
3: X
OUT pin is excluded.
SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
350
400
50
50
50
50
50
50
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK1
)/2–50
t
c(S
CLK2
)/2–240
t
c(S
CLK1
)/2–50
t
c(S
CLK2
)/2–240
–30
0
20
20
Typ. Max.
t
wH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t
d(S
CLK1
–T
X
D)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK1
–T
X
D)
t
v(S
CLK2
–S
OUT2
)
tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 36
Note1: When the P4
5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P5
1/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.
3: X
OUT pin is excluded.
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