Renesas V850E2 Manuel d'utilisateur Page 56
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- Table des matières
- MARQUE LIVRES
- V850E2/FG4 1
- R01DS0139ED0100 2
- Data Sheet 2
- Regional Information 5
- Notes for CMOS Devices 6
- Table of contents 7
- Chapter 1 Overview 9
- Load on test: 10
- 2.1 Supply voltages 11
- 2.2 Port voltages 12
- 2.3 Port current 13
- 2.4 Capacitance 13
- 2.5 Thermal characteristics 14
- 3.2 Power area definitions 15
- 3.3 Power supply groups 16
- 3.4 Supply voltages 17
- During power-up sequence 18
- After DeepStop mode 18
- 3.4.4 POC characteristics 21
- 3.5.2 Condition 1 22
- 3.5.3 Condition 2 23
- 3.5.4 Condition 5 24
- 3.5.5 Condition 6 25
- Chapter 4 Clock generators 26
- 4.3.2 Sub-oscillator 27
- 4.3.3 Internal oscillator 28
- 4.4 PLL Characteristics 29
- Chapter 5 I/O specification 30
- 5.1.2 PgE0 31
- 5.1.3 PgE1 32
- 5.1.4 PgB0 33
- 5.1.5 PgA0 33
- Chapter 5 I/O specification 34
- 7.1 Reset timing 37
- 7.2 NMI timing 37
- 7.3 INTP timing 38
- 7.4 FLMD0 timing 38
- 7.5 _DCUTRST timing 38
- 7.6 Timer timing 39
- 7.7 CSI timing 41
- CSIGnRYI 44
- CSIHnRYI 44
- CSIHnCSS0-7 45
- 7.7.2 Slave mode 47
- CSIGnRYO 49
- CSIHnRYO 49
- CSIHnTIC 49
- 7.8 UART timing 50
- 7.9 FCN timing 51
- 7.10 FlexRay timing 52
- RISE-FALL 53
- 7.11 IIC timing 54
- 7.13 VLVI characteristics 56
- 7.15 LVI characteristics 58
- 7.17 Key Return 66
- 8.1 Code flash specification 67
- 8.2 Data flash specification 67
- 9.2 Package specification 70
- Digital output 72
- Quantization error 73
- Analog input 73
- AVREFPAVREFM 74
- Ideal linearity 77
- Integral linearity error 77
- Revision History 78
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