Renesas V850E2 Manuel d'utilisateur Page 42
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- Table des matières
- MARQUE LIVRES
- V850E2/FJ4-L 1
- R01DS0148EJ0102 2
- Data Sheet 2
- Regional Information 5
- Notes for CMOS Devices 6
- Chapter 1 Overview 9
- 10
- 2.1 Supply voltages 11
- 2.2 Port voltages 11
- 2.3 Port current 12
- 2.4 Capacitance 13
- 2.5 Thermal characteristics 13
- 3.2 Power area definitions 14
- 3.3 Power supply groups 15
- 3.4 Supply voltages 16
- System supply voltage 17
- Note n=1-2 18
- 3.4.3 POC characteristics 19
- 3.5.2 Condition 1 20
- 3.5.3 Condition 2 21
- 3.5.4 Condition 3 22
- Chapter 4 Clock generators 23
- 4.3.1 Main oscillator 24
- 4.4 PLL Characteristics 25
- Chapter 5 I/O specification 26
- Chapter 5 I/O specification 27
- 5.1.2 PgE0 28
- 5.1.3 PgE1 29
- 5.1.4 PgA0 30
- • Ta = 25°C 31
- 7.1 Reset timing 32
- 7.2 NMI timing 32
- 7.3 INTP timing 33
- 7.4 FLMD0 timing 33
- 7.5 _DCUTRST timing 33
- 7.6 Timer timing 34
- 7.7 CSI timing 35
- 7.7.2 Slave mode 38
- CSIGnRYO 40
- 7.8 UART timing 41
- 7.9 FCN timing 42
- 7.10 IIC timing 43
- 7.11 VLVI characteristics 45
- 7.12 LVI characteristics 46
- 7.13.1 10bit A/D 47
- 7.14 Key Return 49
- 7.15 DPIN (SEQ Digital Input) 49
- 8.1 Code flash specification 50
- 8.2 Data flash specification 50
- 9.2 Package specification 52
- Revision History 53
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