Renesas V850E2 Manuel d'utilisateur télécharger pdf (Page 43)

R01DS0148EJ0102

Data Sheet

Chapter 7 Peripherals specification

7.10 IIC timing

Table 7-4 Normal mode

Parameter Symbol Condition

Ratings

Unit

Min Typ Max

SCL clock period fCLK 0 100 kHz

Bus free time (between stop condition

and start condition)

tBUF 4.7 - - µs

Start/Restart Hold time (New clock

pulse

is generated after this hold time as a

master.)

tHD:STA 4 - - µs

SCL clock low state hold time tLOW 4.7 - - µs

SCL clock high state hold time tHIGH 4 - - µs

Setup time for start/restart condition tSU:STA 4.7 - - µs

Data hold time tHD:DAT

CBUS compatible 5 - - µs

IIC bus 0 - - µs

Data setup time tSU:DAT 250 - - ns

Rising transition time of SDA or SCL tR - - 1000 ns

Falling transition time of SDA or SCL tF - - 300 ns

Setup time of stop condition tSU:STO 4 - - µs

Bus capacitance Cb - - 400 pF

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 52 53

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Renesas V850E2 Manuel d'utilisateur Page 43