Renesas PROM Programming Adapters PCA7438F-64A Spécifications Page 12

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Vue de la page 11
Rev.2.40 Jun 14, 2004 page 12 of 56
38C1 Group
Fig. 10 Memory map of special function register (SFR)
0
0
0
0
1
6
0
0
2
0
1
6
0
0
0
1
1
6
0
0
2
1
1
6
0
0
0
2
1
6
0
0
2
2
1
6
0
0
0
3
1
6
0
0
2
3
1
6
0
0
0
4
1
6
0
0
2
4
1
6
0
0
0
5
1
6
0
0
2
5
1
6
0
0
0
6
1
6
0
0
2
6
1
6
0
0
0
7
1
6
0
0
2
7
1
6
0
0
0
8
1
6
0
0
2
8
1
6
0
0
0
9
1
6
0
0
2
9
1
6
0
0
0
A
1
6
0
0
2
A
1
6
φ output control register
0
0
0
B
1
6
0
0
2
B
1
6
0
0
0
C
1
6
0
0
2
C
1
6
T
e
m
p
o
r
a
r
y
d
a
t
a
r
e
g
i
s
t
e
r
1
(
T
D
0
)
000D
16
002D
16
Temporary data register 2 (TD1)
0
0
0
E
1
6
0
0
2
E
1
6
T
e
m
p
o
r
a
r
y
d
a
t
a
r
e
g
i
s
t
e
r
3
(
T
D
2
)
0
0
0
F
1
6
0
0
2
F
1
6
R
R
F
r
e
g
i
s
t
e
r
(
R
R
F
)
0010
16
LCD display register 0(LCD
0
)
0030
16
0
0
1
1
1
6
LCD display register 1(LCD
1
)
0
0
3
1
1
6
0
0
1
2
1
6
0
0
3
2
1
6
0013
16
0033
16
0
0
1
4
1
6
0
0
3
4
1
6
0015
16
0035
16
0
0
1
6
1
6
0
0
3
6
1
6
0
0
1
7
1
6
0
0
3
7
1
6
0018
16
0038
16
0
0
1
9
1
6
0
0
3
9
1
6
0
0
1
A
1
6
0
0
3
A
1
6
001B
16
003B
16
0
0
1
C
1
6
0
0
3
C
1
6
0
0
1
D
1
6
0
0
3
D
1
6
0
0
1
E
1
6
0
0
3
E
1
6
0
0
1
F
1
6
0
0
3
F
1
6
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
2
(
L
C
D
2
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
3
(
L
C
D
3
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
4
(
L
C
D
4
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
5
(
L
C
D
5
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
6
(
L
C
D
6
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
7
(
L
C
D
7
)
LCD display register 8(LCD
8
)
LCD display register 9(LCD
9
)
LCD display register 10(LCD
10
)
LCD display register 11(LCD
11
)
LCD display register 12(LCD
12
)
P
o
r
t
P
0
(
P
0
)
Port P2 (P2)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
4
,
A
D
K
E
Y
p
i
n
s
e
l
e
c
t
i
o
n
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
P
o
r
t
P
5
(
P
5
)
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
5
D
)
P
o
r
t
P
6
(
P
6
)
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
6
D
)
Interrupt control register 2(ICON2)
Timer 3 (T3)
Timer X mode register (TXM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Timer X (low) (TXL)
Timer Y (low) (TYL)
Timer 1 (T1)
Timer 2 (T2)
Timer X (high) (TXH)
Timer Y (high) (TYH)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
Segment output enable register (SEG)
LCD mode register (LM)
A/D control register (ADCON)
A/D conversion register (AD)
Port P3 direction register (P3D)
S
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
C
O
N
)
S
e
r
i
a
l
I
/
O
r
e
g
i
s
t
e
r
(
S
I
O
)
PULL register
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