Renesas PROM Programming Adapters PCA7438F-64A Spécifications Page 21
- Page / 59
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Rev.2.40 Jun 14, 2004 page 21 of 56
38C1 Group
TIMERS
The 38C1 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
Fig. 18 Timer block diagram
"1"
P53/CNTR1
"0"
"10"
"00","01","11"
P
52/
C
N
T
R0
Q
Q
T
S
P52 direction register
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
P
52
l
a
t
c
h
"0"
"
1
"
"
0
"
"1"
"10"
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R
0
e
d
g
e
s
w
i
t
c
h
b
i
t
Q
Q
T
S
"0"
P62 direction register
P6
2 latch
"0"
"1"
T
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
"0"
"
1
"
T
OUT output
control bit
"
1
"
P
6
2/
TO
U
T
f
(
XC
I
N)
"0"
"1"
TO
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
φS
O
U
R
C
E/
1
6
"
1
1
"
φS
O
U
R
C
E/
1
6
"
1
"
"0"
Count source selection bit (Note 1)
φS
O
U
R
C
E
φSOURCE/16
φ
SOURCE/16
f
(
XI
N)
/
1
6
(
N
o
t
e
2
)
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
1
)
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
Timer Y stop
control bit
Falling edge detection
Period
measurement mode
Timer Y
interrupt
request
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
l
y
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Rising edge detection
Timer Y
operating
mode bits
(Note 1)
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Timer X stop
control bit
Timer X write
control bit
Timer X operat-
ing mode bits
“00”,“01”,“11”
CNTR0 active
edge switch bit
Timer 2 write
control bit
T
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
1
)
Timer 2
interrupt
request
Timer 3
interrupt
request
Timer 2 count source
selection bit
(Note 1)
Timer 1
interrupt
request
D
a
t
a
b
u
s
Timer Y (low) (8) Timer Y (high) (8)
T
i
m
e
r
3
l
a
t
c
h
(
8
)
Timer 3 (8)
Timer 1 latch (8)
T
i
m
e
r
1
(
8
)
Timer 2 latch (8)
Timer 2 (8)
T
i
m
e
r
X
(
l
o
w
)
(
8
)
Timer X (high) (8)
T
i
m
e
r
X
(
l
o
w
)
l
a
t
c
h
(
8
)
Timer X (high) latch (8)
T
i
m
e
r
Y
(
l
o
w
)
l
a
t
c
h
(
8
)T
i
m
e
r
Y
(
h
i
g
h
)
l
a
t
c
h
(
8
)
Timer Y operating mode bits
“00”,“01”,“10”
CNTR0
interrupt
request
C
N
T
R1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
φ
S
O
U
R
C
E:
r
e
p
r
e
s
e
n
t
s
t
h
e
s
u
p
p
l
y
s
o
u
r
c
e
o
f
i
n
t
e
r
n
a
l
c
l
o
c
k
φ.
I
t
i
s
t
h
e
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
o
f
XI
N
i
n
p
u
t
i
n
t
h
e
m
i
d
d
l
e
-
a
n
d
h
i
g
h
-
s
p
e
e
d
m
o
d
e
,
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
i
n
t
h
e
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
e
,
a
n
d
s
u
b
-
c
l
o
c
k
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
.
N
o
t
e
s
1
:
I
n
t
e
r
n
a
l
c
l
o
c
k
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
i
s
t
h
e
s
u
b
-
c
l
o
c
k
o
s
c
i
l
l
a
t
i
o
n
/
2
.
I
n
t
e
r
n
a
l
c
l
o
c
k
i
n
t
h
e
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
e
i
s
t
h
e
i
n
t
e
r
n
a
l
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
o
s
c
i
l
l
a
t
i
o
n
/
8
.
E
x
c
e
p
t
C
N
T
R
i
n
p
u
t
,
t
i
m
e
r
1
a
n
d
t
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
,
t
h
e
c
l
o
c
k
e
x
c
e
p
t
s
y
s
t
e
m
c
l
o
c
k
c
a
n
n
o
t
b
e
u
s
e
d
a
s
t
h
e
c
o
u
n
t
s
o
u
r
c
e
.
2
: φ
S
O
U
R
C
E
c
a
n
b
e
s
e
l
e
c
t
e
d
a
s
t
h
e
t
i
m
e
r
X
c
o
u
n
t
s
o
u
r
c
e
o
n
l
y
i
n
t
h
e
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
.
W
r
i
t
e
“
0
”
t
o
t
h
e
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
e
x
c
e
p
t
i
n
t
h
e
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
.
- 38C1 Group 1
- PIN CONFIGURATION (TOP VIEW) 2
- FUNCTIONAL BLOCK DIAGRAM 3
- PIN DESCRIPTION 4
- PART NUMBERING 5
- GROUP EXPANSION 6
- Memory Type 6
- Memory Size 6
- Packages 6
- I/O PORTS 13
- Pull-up/Pull-down Control 13
- INTERRUPTS 18
- Interrupt Control 18
- Interrupt Operation 18
- Timer 1, Timer 2, Timer 3 24
- ■Note on Timer 1 to Timer 3 24
- Serial I/O 25
- ADKEY Control Circuit 28
- LCD DRIVE CONTROL CIRCUIT 30
- Power Input Pins 32
- LCD Display register 33
- LCD Drive Timing 33
- OTHER FUNCTION REGISTERS 36
- RESET CIRCUIT 37
- N.G. O.K 43
- ROM PROGRAMMING METHOD 45
- DATA REQUIRED FOR MASK ORDERS 45
- ELECTRICAL CHARACTERISTICS 46
- Absolute Maximum Ratings 46
- CIN) < f(XIN)/3 49
- IN), the rating 49
- Electrical Characteristics 50
- IN) ≥ 500 kHz 52
- OUT, XCOUT pins are excluded 54
- PACKAGE OUTLINE 56
- 3 = 1 → CM3 = * (Note 9) 57
- RENESAS SALES OFFICES 59
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