Renesas PROM Programming Adapter PCA7435FPG02 Spécifications télécharger pdf (Page 20)

7534 Group

Rev.3.00 Oct 23, 2006 page 20 of 53

REJ03B0099-0300

Fig. 21 Block diagram of timer X, timer 1 and timer 2

Timer mode

pulse output mode

To timer X

interrupt

request bit

f(XIN)/16

Timer X latch (8)

Timer X (8)

Prescaler X latch (8)

Prescaler X (8)

Pulse width

measurement

mode

f(XIN)/2

Timer X count

source selection bit

Event

counter

mode

Timer X count stop bit

Port P14 direction

“0”

“1”

CNTR

active

edge switch bit

Port P14 latch

Pulse output mode

“1”

“0”

CNTR

active

edge switch bit

P14/CNTR0

Toggle

flip-flop

Timer X latch write

Pulse output mode

To CNTR0

interrupt

request bit

Data bus

To timer 1

interrupt

request bit

To timer 2

interrupt

request bit

Data bus

Prescaler 12 (8)

f(XIN)/16

Timer 1 (8) Timer 2 (8)

Timer 2 latch (8)Timer 1 latch (8)Prescaler 12 latch (8)

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 55 56

7534 Group 1
PIN CONFIGURATION (TOP VIEW) 2
FUNCTIONAL BLOCK 4
High-order 16
Low-order 16
3 as input ports 18
Serial Interface 21
●Serial I/O1 21
1/TxD pin 22
OUT pin for the USB reference 23
16) the serial I/O2 31
A/D Converter 32
REF pin and VSS 32
7/AN7 to P20/AN0, and 32
ROM PROGRAMMING METHOD 40
ELECTRICAL CHARACTERISTICS 41
Absolute Maximum Ratings 41
0–P07, P10–P16, P20–P27, P30– 41
Electrical Characteristics 43
A/D Converter Characteristics 44
Measured 45
CMOS output 45
REJ03B0099-0300 49
Outline PLQP0032GB-A 50
Outline PRDP0042BA-A 51
PACKAGE OUTLINE 52
____________ 54
Oct. 23, 2006 55
RENESAS SALES OFFICES 56

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Renesas PROM Programming Adapter PCA7435FPG02 Spécifications Page 20

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