Renesas PROM Programming Adapter PCA7435FPG02 Spécifications télécharger pdf (Page 45)

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Rev.3.00 Oct 23, 2006 page 45 of 53

REJ03B0099-0300

Timing Requirements

Table 12 Timing requirements (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Min. Typ. Max.

Symbol Parameter

Limits

Unit

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tC(CNTR)

tWH(CNTR)

tWL(CNTR)

tC(SCLK)

tWH(SCLK)

tWL(SCLK)

tsu(SDATA–SCLK)

th(SCLK–SDATA)

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR

0 input cycle time

CNTR0, INT0, INT1 input “H” pulse width

CNTR0, INT0, INT1 input “L” pulse width

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

Serial I/O2 input hold time

166

200

1000

400

200

µs

Switching Characteristics

Table 13 Switching characteristics (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Min. Typ. Max.

Symbol Parameter

Limits

Unit

tWH(SCLK)

tWL(SCLK)

td(SCLK–SDATA)

tv(SCLK–SDATA)

tr(SCLK)

tf(SCLK)

tr(CMOS)

tf(CMOS)

tr(D+), tr(D-)

tf(D+), tf(D-)

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output rising time

Serial I/O2 clock output falling time

CMOS output rising time (Note)

CMOS output falling time (Note)

USB output rising time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =

4.4 to 5.25 V

USB output falling time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =

4.4 to 5.25 V

150

Notes: XOUT pin is excluded.

Fig. 51 Output switching characteristics measurement circuit

100 pF

Measured

output pin

CMOS output

tC(SCLK)/2–30

140

300

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 55 56

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Renesas PROM Programming Adapter PCA7435FPG02 Spécifications Page 45

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