Renesas R8C/17 Guide de l'utilisateur télécharger pdf (Page 89)

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When the contents of registers, TRD0 and TRDGRA0 matches, the timer regis-

ters start counting downwards. During this downward counting, all the outputs get

inactive levels for all the match conditions.

The PWM period signal gets toggled whenever the timer register, TRD0 matches

with the value of TRDGRA0.

Combining Analog to Digital Converter with this PWM Mode:

There is a facility to start AD conversion when the compare match is established

between TRD0 and TRDGRA0 and the underflow of TDR1 register. This feature is

very much required for many power managing algorithms.

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Renesas R8C/17 Guide de l'utilisateur Page 89