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Renesas PROM Programming Adapter PCA7435FPG02 Manuel d'utilisateur Page 47

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Vue de la page 46
7540 Group
Rev.4.00 Jun 21, 2004 page 47 of 82
REJ03B0011-0400Z
Fig. 53 State transition
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Oscillation stop detection circuit valid
CPUM4←12
MISRG1←12
I
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u
p
t
Interrupt
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WIT
instruction
I
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p
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M
I
S
R
G1←02
CPUM3←12
CPUM3←02
C
P
U
M7
6←1
02
C
P
U
M7
6←0
02
0
12
1
12
(
N
o
t
e
2
)
CPUM
4←02
M
I
S
R
G1←12 M
I
S
R
G1←02
R
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1
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:
f
(X
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)
(
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1
)
f
(X
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)
o
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O
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2
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:
f
(X
I
N
)
(
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1
)
f
(X
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N
)
o
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State 3
Operation clock source:
On-chip oscillator (Note 3)
f(X
IN
) oscillation enabled
On-chip oscillator enalbed
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4
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:
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3
)
f
(X
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)
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Notes on switch of clock
(1) In operation clock source = f(X
IN
), the following can be
selected for the CPU clock division ratio.
● f(X
IN
)/2 (high-speed mode)
● f(X
IN
)/8 (middle-speed mode)
● f(X
IN
) (double-speed mode, only at a ceramic oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing X
IN
oscillation.
(3) In operation clock source = on-chip oscillator, the middle-
speed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
• CPUM76 → 10
2
(State 2 → state 3)
• NOP instruction
• CPUM4 → 1
2
(State 3 → state 4)
Double-speed mode at on-chip oscillator: NOP ✕ 3
High-speed mode at on-chip oscillator: NOP ✕ 1
Middle-speed mode at on-chip oscillator: NOP ✕ 0
Reset state
C
P
U
M7
6←1
02
C
P
U
M7
6←0
02
0
12
1
12
(
N
o
t
e
2
)
S
t
a
t
e
2
’
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:
f
(X
I
N
)
(
N
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1
)
O
n
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State 3’
Operation clock source:
On-chip oscillator (Note 3)
f(X
IN
) oscillation enabled
On-chip oscillator enalbed
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