
7540 Group
Rev.4.00 Jun 21, 2004 page 70 of 82
REJ03B0011-0400Z
Switching characteristics measurement circuit diagram (Gen-
eral purpose)
/ / /
Measured
output pin
CMOS output
100 pF
Switching Characteristics (Extended operating temperature version)
Table 28 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–30
tC(SCLK2)/2–30
0
Min. Typ. Max.
Symbol Parameter
Limits
Unit
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Note 1: Pin XOUT is excluded.
Table 29 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter
Limits
Unit
350
50
50
350
50
50
50
50
Note 1: Pin XOUT is excluded.
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–50
tC(SCLK2)/2–50
0
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
140
30
30
140
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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