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Renesas PCA7429G02 Informations techniques Page 34

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Vue de la page 33
31
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.2 I
2
C Address Register
The I
2
C address register (address 00F716) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I
2
C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
Fig. 8.6.3 I
2
C Address Register
b
7b
6b
5b
4b
3b
2b
1b
0
0R
e
a
d
/
w
r
i
t
e
b
i
t
(
R
B
W
)
1
t
o
7
S
l
a
v
e
a
d
d
r
e
s
s
(
S
A
D
0
t
o
S
A
D
6
)
<
O
n
l
y
i
n
1
0
-
b
i
t
a
d
d
r
e
s
s
i
n
g
(
i
n
s
l
a
v
e
)
m
o
d
e
>
T
h
e
l
a
s
t
s
i
g
n
i
f
i
c
a
n
t
b
i
t
o
f
a
d
d
r
e
s
s
d
a
t
a
i
s
c
o
m
p
a
r
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d
.
0
:
W
a
i
t
t
h
e
f
i
r
s
t
b
y
t
e
o
f
s
l
a
v
e
a
d
d
r
e
s
s
a
f
t
e
r
S
T
A
R
T
c
o
n
d
i
t
i
o
n
(
r
e
a
d
s
t
a
t
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)
1
:
W
a
i
t
t
h
e
f
i
r
s
t
b
y
t
e
o
f
s
l
a
v
e
a
d
d
r
e
s
s
a
f
t
e
r
R
E
S
T
A
R
T
c
o
n
d
i
t
i
o
n
(
w
r
i
t
e
s
t
a
t
e
)
<
I
n
b
o
t
h
m
o
d
e
s
>
T
h
e
a
d
d
r
e
s
s
d
a
t
a
i
s
c
o
m
p
a
r
e
d
.
I
2
C
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
I
2
C
a
d
d
r
e
s
s
r
e
g
i
s
t
e
r
(
S
0
D
)
[
A
d
d
r
e
s
s
0
0
F
7
1
6
]
B
N
a
m
e
F
u
n
c
t
i
o
n
s
0
0
A
f
t
e
r
r
e
s
e
t
R
W
R—
R
W
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