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Renesas PCA7429G02 Informations techniques Page 71

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68
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
The horizontal display start position is common to all blocks, and can
be set in 128 steps (where 1 step is 4T
OSC, TOSC being the OSD
oscillation cycle) as values “00
16” to “FF16” in bits 0 to 6 of the hori-
zontal position register (address 00D1
16). The horizontal position reg-
ister is shown in Figure 8.11.8.
Fig. 8.11.8 Horizontal Position Register
Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs
between the horizontal display start position set by the horizontal
position register and the most left dot of the 1st block. Accordingly,
when 2 blocks have different pre-divide ratios, their horizontal dis-
play start position will not match.
2 : The horizontal start position is based on the OSD clock source cycle
selected for each block. Accordingly, when 2 blocks have different
OSD clock source cycles, their horizontal display start position will
not match.
3 : When setting “00
16” to the horizontal position register, it needs ap-
proximately 62T
OSC (= Tdef) interval from a rising edge (when nega-
tive polarity is selected) of H
SYNC signal to the horizontal display start
position.
Fig. 8.11.9 Notes on Horizontal Display Start Position
4
T
O
S
C
’
✕
N
4
T
O
S
C
✕
N
H
S
Y
N
C
1
T
C
1
T
C
1
T
C
N
o
t
e
1
N
o
t
e
2
B
l
o
c
k
2
(
P
r
e
-
d
i
v
i
d
e
r
a
t
i
o
=
2
,
c
l
o
c
k
s
o
u
r
c
e
=
d
a
t
a
s
l
i
c
e
r
c
l
o
c
k
)
B
l
o
c
k
3
(
P
r
e
-
d
i
v
i
d
e
r
a
t
i
o
=
3
,
c
l
o
c
k
s
o
u
r
c
e
=
d
a
t
a
s
l
i
c
e
r
c
l
o
c
k
)
B
l
o
c
k
4
(
P
r
e
-
d
i
v
i
d
e
r
a
t
i
o
=
3
,
c
l
o
c
k
s
o
u
r
c
e
=
O
S
C
1
)
T
d
e
f
T
d
e
f
’
N:
V
a
l
u
e
o
f
h
o
r
i
z
o
n
t
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
(
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
)
1
T
C
:
O
S
D
c
l
o
c
k
c
y
c
l
e
d
i
v
i
d
e
d
i
n
p
r
e
-
d
i
v
i
d
e
c
i
r
c
u
i
t
T
O
S
C
:
O
S
D
o
s
c
i
l
l
a
t
i
o
n
c
y
c
l
e
T
d
e
f
:
6
2
T
O
S
C
b7 b6 b5b4 b3 b2b1 b0
Horizontal position register (HP) [Address 00D1
16
]
B Name
Horizontal Position Register
7
Horizontal display start
position control bits
(HP0 to HP6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
Functions After reset R W
Horizontal display start positions
128 steps (00
16
to 7F
16
)
(1 step is 4T
OSC
)
0
0
RW
R—
0
to
6
Note: The setting value synchronizes with the V
SYNC
.
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