Renesas PROM Programming Adapter PCA7408 Manuel d'utilisateur Page 42
- Page / 112
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 42 of 110
REJ03B0134-0100Z
Fig. 8.6.12 Address Data Communication Format
SS
l
a
v
e
a
d
d
r
e
s
s
A
D
a
t
aAD
a
t
aA
/
A PR
/
W
7
b
i
t
s“
0
”1
t
o
8
b
i
t
s1 to 8 bits
SS
l
a
v
e
a
d
d
r
e
s
s
A
D
a
t
a AD
a
t
a AP
7
b
i
t
s“
1
”1
t
o
8
b
i
t
s1 to 8 bits
(
1
)
A
m
a
s
t
e
r
-
t
r
a
n
s
m
i
t
t
e
r
t
r
a
n
s
m
i
t
s
d
a
t
a
t
o
a
s
l
a
v
e
-
r
e
c
e
i
v
e
r
S
S
l
a
v
e
a
d
d
r
e
s
s
1
s
t
7
b
i
t
s
A
A
D
a
t
a
7
b
i
t
s“
0
”8
b
i
t
s1 to 8 bits
(2) A master-receiver receives data from a slave-transmitte
r
S
l
a
v
e
a
d
d
r
e
s
s
2
n
d
b
y
t
e
A
D
a
t
aA
/
A P
1
t
o
8
b
i
t
s
S
S
l
a
v
e
a
d
d
r
e
s
s
1
s
t
7
b
i
t
s
A
A
7
b
i
t
s“
0
”8
b
i
t
s7 bit
s
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
l
a
v
e
a
d
d
r
e
s
s
2
n
d
b
y
t
e
Data
1 to 8 bits
Sr
Slave address
1st 7 bits
A
Data
A
P
1
t
o
8
b
i
t
s“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S:START conditionP : STOP condition
A:ACK bit R/W : Read/Write bit
Sr : Restart condition
From master to slave
From slave to master
R
/
W
R
/
W
R/W R/W
8.6.12 Precautions when using multi-master
I
2
C-BUS interface
(1) Read-modify-write instruction
Precautions for executing the read-modify-write instructions such as
SEB, and CLB, is for each register of the multi-master I
2
C-BUS inter-
face are described below.
•I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become an arbitrary value.
•I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detection of the STOP condition, data may become an arbitrary
______
value. It is because hardware changes the read/write bit (RBW) at
the timing.
•I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
•I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detection of the START condition or at completion the byte trans-
fer, data may become an arbitrary value. Because hardware changes
the bit counter (BC0–BC2) at the timing.
•I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generation procedure us-
ing multi-master
➀ Procedure example (The necessary conditions for the procedure
are described in ➁ to ➄ below).
•
•
LDA — (Take out slave address value)
SEI (Interrupt disabled)
BBS 5,S1,BUSBUSY
(BB flag confirmation and branch process)
BUSFREE:
STA S0 (Write slave address value)
LDM #$F0, S1
(Trigger START condition generation)
CLI (Interrupt enabled)
•
•
BUSBUSY:
CLI (Interrupt enabled)
•
•
➁ Use “STA,” “STX” or “STY” of the zero page addressing instruc-
tion for writing the slave address value to the I
2
C data shift register.
➂ Use “LDM” instruction for setting trigger of START condition gen-
eration.
④ Write the slave address value of ➁ and set trigger of START con-
dition generation as in ➂ continuously as shown in the procedure
example.
➄ Disable interrupts during the following three process steps:
• BB flag confirmation
• Write of slave address value
• Trigger of START condition generation
When the condition of the BB flag is bus busy, enable interrupts
immediately.
- 1. DESCRIPTION 0
- 2. FEATURES 0
- 3. APPLICATION 0
- REJ03B0134-0100Z 1
- Address 00E016 2
- Addresses 00DE16 and 00DF16 2
- Addresses 00E116 and 00E216 3
- Address 00E416 3
- Addresses 00E616 to 00E916 4
- Address 00E516 4
- Address 00EA16 5
- Addresses 00EC16 5
- Address 00ED16 6
- Addresses 00EE16 6
- Address 00EF16 7
- Addresses 00F416 7
- Address 00F516 8
- Addresses 00F916 8
- Address 00FB16 9
- Addresses 00FC16 9
- Address 00FD16 10
- Addresses 00FE16 10
- Address 00FF16 11
- Addresses 021B16 11
- 42P2R-A/E 13
- REVISION HISTORY 14
- RENESAS SALES OFFICES 15
- 8. FUNCTION BLOCK DESCRIPTION 16
- 8.1.1 CPU Mode Register 16
- RCR1 RCR0 21
- TABLE OF CONTENTS 24
- (4) Serial I/O interrupt 25
- (5) f(XIN)/4096 interrupt 25
- (6) Multi-master I 25
- C-BUS interface interrupt 25
- (7) BRK instruction interrupt 25
- 8.4 TIMERS 29
- 8.4.1 Timer 1 29
- 8.4.2 Timer 2 29
- 8.4.3 Timer 3 29
- 8.4.4 Timer 4 29
- Timer 34 Mode Register 30
- 8.5 SERIAL I/O 32
- 16), and the transfer 33
- OUT pin. Transfer 33
- 4. PIN CONFIGURATION 35
- Outline 42P4B 35
- Outline 42P2R-A/E 35
- 8.6 MULTI-MASTER I 37
- C-BUS INTERFACE 37
- C Data Shift Register 38
- C Address Register 39
- 16) is used to set ACK 40
- C Control Register 42
- (1) 7-bit addressing format 47
- (2) 10-bit addressing format 47
- (5) Writing to I 50
- C status register 50
- 8.8 A-D COMPARATOR 56
- 5. FUNCTIONAL BLOCK DIAGRAM 57
- 8.9 D-A CONVERTER 59
- 8.10 ROM CORRECTION FUNCTION 61
- 8.11 OSD FUNCTIONS 62
- OSD Control Register 65
- 8.11.1 Display Position 66
- 6. PERFORMANCE OVERVIEW 68
- Vertical Position Register i 69
- Horizontal Position Register 70
- 8.11.2 Character Size 71
- 8.11.3 Clock for OSD 73
- 8.11.4 Memory for OSD 74
- Border Selection Register 80
- 8.11.7 Multiline Display 81
- 8.11.8 OSD Output Pin Control 82
- 8.13. RESET CIRCUIT 85
- 8.14 CLOCK GENERATING CIRCUIT 86
- 8.17 ADDRESSING MODE 87
- 8.18 MACHINE INSTRUCTIONS 87
- 9. TECHNICAL NOTES 87
- 8.16 AUTO-CLEAR CIRCUIT 87
- 10. ABSOLUTE MAXIMUM RATINGS 88
- 7. PIN DESCRIPTION 90
- + Power source voltage 91
- 15. MULTI-MASTER I 92
- 16. PROM PROGRAMMING METHOD 93
- M37221EASP 95
- M37221EAFP 95
- 19. APPENDIX 96
- Pin Configuration (TOP VIEW) 96
- Memory Map 98
- Register (SFR) 100
- Program Counter at Reset 104
- Structure of Register 105
- Address 00C716 106
- Address 00CB16 107
- Address 00CD16 107
- Address 00D516 108
- Address 00D616 108
- Address 00D816 109
- Address 00D716 109
- Address 00D916 110
- Address 00DA16 110
- Address 00DB16 111
- Address 00DC16 111
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