R8C/10 Group 13. Serial InterfaceI
Rev.1.20 Jan 27, 2006 page 92 of 180
REJ09B0019-0120
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
m
o
d
e
r
e
g
i
s
t
e
r
(
i
=
0
,
1
)
Symbol Address After reset
U0MR 00A0
16
00
16
U1MR 00A8
16
00
16
b
7b6b
5b
4b
3b
2b
1b
0
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
R
W
C
K
D
I
R
S
M
D
1
S
M
D
0
S
e
r
i
a
l
i
n
t
e
r
f
a
c
e
m
o
d
e
s
e
l
e
c
t
b
i
t
(2
)
S
M
D
2
Internal/external clock
select bit
(3)
S
T
P
S
P
R
Y
PRYE
(b7)
Parity enable bit
0 : Internal clock
1 : External clock
(1)
Stop bit length select bit
Odd/even parity select bit
Reserved bit
0
:
1
s
t
o
p
b
i
t
1
:
2
s
t
o
p
b
i
t
s
0
:
P
a
r
i
t
y
d
i
s
a
b
l
e
d
1
:
P
a
r
i
t
y
e
n
a
b
l
e
d
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
b2 b1 b0
E
f
f
e
c
t
i
v
e
w
h
e
n
P
R
Y
E
=
1
0
:
O
d
d
p
a
r
i
t
y
1
:
E
v
e
n
p
a
r
i
t
y
Set to “0”
F
u
n
c
t
i
o
n
NOTES:
1. Must set the P1_6 bit in the PD1 register to “0” (input).
2. For the U1MR register, the SMD2 to SMD0 bits must not be set except the followings: “000
2
”, “100
2
”, “101
2
”, or “110
2
”.
3. Must set the CKDIR bit to “0” (internal clock) in UART1.
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
i
=
0
,
1
)
Symbol Address After reset
U0C0 00A4
16
08
16
U1C0 00AC
16
08
16
b
7b
6b
5b
4b
3b
2b
1b
0
F
u
n
c
t
i
o
n
TXEPT
CLK1
CLK0
(b2)
NCH
CKPOL
BRG count source
select bit
(1)
Transmit register empty
flag
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CLK polarity select bit
Data output select bit
0 0 : f
1SIO
is selected
0 1 : f
8SIO
is selected
1 0 : f
32SIO
is selected
1 1 : Avoid this setting
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
Nothing is assigned.
When write, set to “0”. When read, its content is indeterminate.
0 : TxDi pin is a pin of CMOS output
1 : TxDi pin is a pin of N-channel open-drain output
U
F
O
R
MT
r
a
n
s
f
e
r
f
o
r
m
a
t
s
e
l
e
c
t
b
i
t
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
R
W
R
W
R
W
R
W
R
W
RW
RW
RW
RW
RW
RW
R
W
RW
R
W
R
W
RO
0
Reserved bit Set to “0”
(
b
4
)
N
O
T
E
S
:
1
.
I
f
t
h
e
B
R
G
c
o
u
n
t
s
o
u
r
c
e
i
s
s
w
i
t
c
h
e
d
,
s
e
t
t
h
e
U
i
B
R
G
r
e
g
i
s
t
e
r
a
g
a
i
n
.
Figure 13.4 U0MR and U1MR Registers and U0C0 and U1C0 Registers
(11 pages)
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