Renesas R8C/Tiny Series Manuel télécharger pdf (Page 113)

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode

Rev.1.20 Jan 27, 2006 page 103 of 180

REJ09B0019-0120

13.2.3 Bit Rate

Divided-by-16 of frequency by the UiBRG (i=0 to 1) register in UART mode is a bit rate.

• When selecting internal clock

Setting value to the UiBRG register = –1

fj : Count source frequency of the UiBRG register (f1SIO, f8SIO and f32SIO)

• When selecting external clock

Setting value to the UiBRG register = –1

fEXT : Count source frequency of the UiBRG register (external clock)

Bit Rate ✕ 16

fEXT

Bit Rate ✕ 16

Figure 13.11 Calculation Formula of UiBRG (i=0 to 1) Register Setting Value

Table 13.7 Bit Rate Setting Example in UART Mode

Bit Rate BRG System Clock = 16MHz System Clock = 8MHz

(bps)

Count Source

BRG Setting Value

Actual Time(bps)

Error(%)

BRG Setting Value

Actual Time(bps)

Error(%)

1200 f8 103 (6716) 1201.92 0.16 51 (3316) 1201.92 0.16

2400 f8 51 (3316) 2403.85 0.16 25 (1916) 2403.85 0.16

4800 f8 25 (1916) 4807.69 0.16 12 (0C16) 4807.69 0.16

9600 f1 103 (6716) 9615.38 0.16 51 (3316) 9615.38 0.16

14400 f1 68 (4416) 14492.75 0.64 34 (2216) 14285.71 –0.79

19200 f1 51 (3316) 19230.77 0.16 25 (1916) 19230.77 0.16

28800 f1 34 (2216) 28571.43 –0.79 16 (1016) 29411.76 2.12

31250 f1 31 (1F16) 31250.00 0.00 15 (0F16) 31250.00 0.00

38400 f1 25 (1916) 38461.54 0.16 12 (0C16) 38461.54 0.16

51200 f1 19 (1316) 50000.00 –2.34 9 (0916) 50000.00 –2.34

1 2 ... 108 109 110 111 112 113 114 115 116 117 118 ... 198 199

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Renesas R8C/Tiny Series Manuel Page 113