C-6
REVISION HISTORY
Rev. Date Description
Page Summary
R8C/10 Group Hardware Manual
1.20
Jan.27.2006
2 Table 1.1 Performance outline revised
3 Figure 1.1 Block diagram partly revised
4 1.4 Product Information, title of Table 1.2
“Product List” → “Product Informaton” revised
Figure 1.2 Type No., Memory Size, and Package partly revised
6 Table 1.3 Pin description revised
7-8 2 Central Processing Unit (CPU) revised
Figure 2.1 CPU register revised
10 Table 4.1 SFR Information(1) NOTES:1 revised
11 Table 4.2 SFR Information(2) NOTES:1 revised
12 Table 4.3 SFR Information(3);
0081
16: “Prescaler Y” → “Prescaler Y Register”
0082
16: “Timer Y Secondary” → “Timer Y Secondary Register”
0083
16: “Timer Y Primary” → “Timer Y Primary Register”
0085
16: “Prescaler Z” → “Prescaler Z Register”
0086
16: “Timer Z Secondary” → “Timer Z Secondary Register”
0087
16: “Timer Z Primary” → “Timer Z Primary Register”
008C
16: “Prescaler X” → “Prescaler X Register” revised
NOTES:1 revised
13 Table 4.4 SFR Information(4) NOTES:1 revised
15 Figure 5.2 Reset Sequence; “72cycles” → “64cycles” revised
17 6 Clock Generation Circuit;
“(oscillation stop detect function)” → “(oscillation stop detection function)” revised
Table 6.1 Clock Generation Circuit Specifications NOTES: 2 deleted
20 Figure 6.3 OCD Register NOTES: 3 partly deleted
22 6.2.1 On-Chip Oscillator Clock;
“The application products ... to accommodate the frequency range.” →
“The application products ... for the frequency change.” revised
24 Table 6.2 Setting Clock Related Bit and Modes CM13 added
28 6.5.1 How to Use Oscillation Stop Detection Function:
“This function cannot ... is below 2 MHz.” added
32 Table 9.1 Bus Cycles for Access Space, Table 9.2 Access Unit and Bus Operation;
“SFR” → “SFR, Data flash”,
ROM/RAM” → “Program ROM/RAM” revised
37 Table 10.2 Relocatable Vector Tables; “A/D” → “A/D Conversion” revised
45 Figure 10.9 Interrupts Priority Select Circuit NOTES: 1 deleted
56 Figure 12.1 Timer X Block Diagram; “Peripheral data bus” → “Data bus” revised
59 Table 12.3 Pulse Output Mode Specifications NOTES: 1 added
73 Figure 12.18 Timer Z Block Diagram; “Peripheral data bus” → “Data bus” revised
91 Figure 13.3 U0TB to U1TB Registers, U0RB and U1RB Registers, and U0BRG and
U1BRG Registers;
UARTi transmit buffer register (i=0, 1) revised
UARTi bit rate register (i=0, 1); NOTES: 3 added
92 Figure 13.4 U0MR to U1MR Registers and U0C0 and U1C0 Registers;
UARTi transmit/receive control register 0 (i=0, 1); NOTES: 1 added
93 Figure 13.5 U0C1 and U1C1 Registers and UCON Register;
UART transmit/receive control register 2; NOTES: 2 added
100 Table 13.5 Registers to Be Used and Settings in UART Mode;
UiBRG: “–” → “0 to 7” revised
105 Figure 14.1 A/D Converter Block Diagram “Vref” → “Vcom” revised
(11 pages)
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