Renesas Single-Chip Microcomputer M34519T-MCU Spécifications télécharger pdf (Page 21)

V850ES-20 MHz

A 16-bit 20 MHz

A 16-bit 16 MHz

B 32-bit 50 MHz

V850ES-20 MHz

A 16-bit 20 MHz

A 16-bit 16 MHz

B 32-bit 50 MHz

3 4

0 0.2 0.4 0.6 0.8 1.0 1.2

1.4

1.6

4.1

1.7

1.0

3.6

0.97

1.00

1.37

1.18

■

Arithmetic processing performance comparison

■

Code size comparison

(Relative comparison)

* Renesas Electronics measurement results using sample program

Cycle time 0.2 µs 0.4 µs

78K0S

78K0

78K0/Kx1

850ES-20 MHz

0.24

0.20

0.05

0.40

78K4

0.125

32-bit RISC

16-bit CISC

8-bit CISC

: 12 MHz (0.168 µs) supported for some products

: 10 MHz (0.2 µs) supported for some products

Minimum instruction execution time

Overview of functions

V850 arithmetic processing performance and code size

Block diagram

Clock gear feature Standby mode

Operating

current

fxx/8

(2.5 MHz)

fxx

(20 MHz)

fxx/32

(625 kHz)

(32.768 kHz)

Operating

frequency

Reduction to 1/400

by switching from main

clock to subclock

Reduction to 1/10th

through clock gear (1/32)

Reduction to 1/5th

through clock gear (1/8)

CPU

Sub

Oscillator

Operating current

Normal

operation mode

HALT mode

IDLE mode

Sub normal

operation mode

Sub IDLE mode

STOP mode

(sub operation)

STOP mode

(sub stop)

Approx. 1/2

Approx. 1/10

Approx. 1/400

Approx. 1/4000

Approx. 1/15000

Operating Stopped

Peripheral

Watch

timer

Main

V850 Benchmark

All Flash MCUs (V850E2/MN4) with 32-bit high-performance CPU cores

The V850 microcontrollers realize high speed, high performance, and high code efciency.

Low Power Consumption

Thanks to a thorough energy-saving design, the V850ES/Jx3-L attains a current/performance ratio of 0.28 mA/MIPS. As a result,

compared with the 32- bit and 16-bit microcontrollers made by other manufacturers and having equivalent performances, the power

consumption is reduced by over 65%.

Lower system power consumption and higher system performance are simultaneously achieved through the V850's extremely high

power performance.

Power performance

mA/MIPS

2.5

Operating current/performance

3.0

Reduction of 27.5%

V850ES/Jx3-L

V850ES/Jx3

16-bit microcontrollers

of competitors

32-bit microcontrollers

of competitors

0.58

0.28

0.80

0.82

Reduction of 65%

16-bit microcontrollers

of competitors

32-bit microcontrollers

of competitors

V850E2M high-performance CPU core: 512 MIPS @ 200 MHz

Products with dual CPU cores achieve world-top-class

performance of 1,024 MIPS when operating at 200 MHz.

Large-capacity ash memory supporting high-speed access:

Max. 2 MB

Many on-chip peripheral functions

Ethernet controller, USB Function/USB Host, and CAN

V850E2M Core

(Single/Dual)

1.2 V (int.) / 3.3 V (ext.)

512MIPS@200MHz / Core

On-chip memory

Package

I/O Port

[In : 7, In/Out : 181]

INTC × 2

* One INTC for each core

DMAC [16ch]

UART [6ch]

UART (FIFO) [4ch]

CSI [6ch]

CSI (FIFO) [4ch]

C [6ch]

CAN [2ch]*

USB FS Function [1ch]

USB FS Host [1ch]

DTS [Max.128ch]

16bit Timer Array

[16ch × 4unit]

32bit Timer Array

[4ch × 1unit]

16bit Encoder Timer

[2ch]

Watchdog Timer

[2ch]*

* Each core uses one channel.

A/D Converter [12ch]

(5 V: 10 bit/3 V: 10 bit)

Debug I/F

Flash memory: 1MB

RAM: 64KB

H bus common memory: 64KB

<Single-core>

Flash memory: 1MB/2MB

RAM: 64KB x 2

H bus common memory: 64KB

<Dual-core>

304 pin FBGA (19mm × 19mm)

Ethernet Controller

[1ch]*

PMEMC (SRAM/SDRAM)

8/16/32-bit

SMEMC (SRAM/SDRAM)

× 16/32-bit

*1. One channel in the µPD70F3510

*2. µPD70F3510, 3512

*3. µPD70F3514, 3515

*4. Not included in the µPD70F3510

Remark: Numbers of channels indicate the total number implemented on the product.

The actual number of usable channels differs depending on multi-use pin settings.

The V850E2/MN4 includes three high-speed internal buses to

maximize the dual-core performance.

These buses allow various types of processing to be

performed in parallel.

By maximizing the performance of each unit in this way, the

overall performance can be dramatically improved.

Example of processing that can be performed in parallel:

<1> Data is transferred at high speed from an external

memory to an Ethernet peripheral by using DMA.

<2> CPU1 executes CAN communication protocol processing

while processing other data at the same time.

<3> CPU2 processes the data from internal RAM2 while

its high-performance CPU core executes high-speed

calculations.

<4>, <5> CPU1 and CPU2 execute no-wait instruction fetches

from the microcontroller's large-capacity ash memory

using the ash cache in each core.

Prism is an analysis and verication environment that provides

software optimized for implementing multi-core architecture.

Prism provides virtual task division, core assignment, and

data-dependent display features that allow software engineers

to easily develop and realize the full potential of multi-core

processors without the need to change the source code.

* Made by CriticalBlue, Inc

<1>

<2>

<5>

<4>

<3>

<5>

<4>

<1> <2> <3> Data ow

<4> <5> Instruction ow

INTC1 RAM1

V850E2M

CPU1

INTC2 RAM2

V850E2M

CPU2

Flash cache 2

Flash cache 1

Flash

memnory

CPU1

bus

CPU2

bus

DMA

bus

DMA

• PMEMC

(SRAM/SDRAM)

For high-speed access

<On-chip peripheral A>

• CSI ∑I

• UART ∑CAN

• A/D, etc.

<On-chip peripheral B>

• EX-RAM

• USB

• Ethernet, etc.

InterfaceInterfaceInterface

Flash interface

Rich development envirenment Introducing Prism*, a dynamic analysis tool for multi-core microcontrollers (V850E2/MN4)

Dual-Core CPUs block diagram

40 41

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 50 51

Commentaires sur ces manuels

Pas de commentaire

Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 21

Commentaires sur ces manuels

Produits connexes et manuels pour Mise en réseau Renesas Single-Chip Microcomputer M34519T-MCU