Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 34
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Noté. / 5. Basé sur avis des utilisateurs
ASSP Lineup (Dashboard Control, Body Control) (5/10)ASSP Lineup (Dashboard Control, Body Control) (4/10)
Generic Name
V850E2/FG4 (Under development)
Part No.
µPD70F3548 µPD70F4000 µPD70F3549 µPD70F4001 µPD70F3550 µPD70F4002
CPU name
V850E2M
CPU performance (Dhrystone)
162 MIPS (@ 80 MHz)
Internal ROM
512 KB (ash) 768 KB (ash) 1 MB (ash)
Internal RAM
48 KB 64 KB 80 KB
Data ash
32 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
104 108 104 108 104 108
External
13
Timer/counter
32-bit timer: 4 ch
×
2 units
16-bit timer: 16 ch
×
2 units
Watchdog timer
2 ch
Serial interface
UART (LIN compatible)
×
5 ch
CSI
×
2 ch
CSI (With FIFO)
×
1 ch
I
2
C
×
1 ch
CAN controller
×
2 ch
FlexRay controller
×
2 ch
×
1 unit*
A/D converter
12 bits
×
20 ch
D/A converter
-
DMA controller
8 ch
Ports I/O
72
Input
-
Debug control unit
Provided (RUN/break/trace)
Other peripheral functions
POC, LVI, clock monitor, comparator, random number generator, data CRC, key return: 8 ch
Operating frequency
When using main clock: 80 MHz (max.)
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.0 V to 5.5 V
Package
100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* µPD70F4000/4001/4002 only
Generic Name
V850E2/FJ4 (Under development)
Part No.
µPD70F3551 µPD70F4003 µPD70F3552 µPD70F4004 µPD70F3553 µPD70F4005 µPD70F3554 µPD70F4006
CPU name
V850E2M
CPU performance (Dhrystone)
162 MIPS (@ 80 MHz)
Internal ROM
512 KB (ash) 768 KB (ash) 1 MB (ash) 1.5 MB (ash)
Internal RAM
48 KB 64 KB 80 KB 112 KB
Data ash
32 KB 64 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
166 170 166 170 166 170 166 170
External
16
Timer/counter
32-bit timer: 4 ch
×
2 units
16-bit timer: 16 ch
×
6 units
Watchdog timer
2 ch
Serial interface
UART (LIN compatible)
×
6 ch
CSI
×
2 ch
CSI (With FIFO)
×
2 ch
I
2
C
×
1 ch
CAN controller
×
3 ch
FlexRay controller
×
2 ch
×
1 unit*
A/D converter
12 bits
×
24 ch
D/A converter
-
DMA controller
8
Ports I/O
109
Input
-
Debug control unit
Provided (RUN/break/trace)
Other peripheral functions
POC, LVI, clock monitor, comparator
×
2, random number generator, data CRC, key return: 8 ch
Operating frequency
When using main clock: 80 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.0 V to 5.5 V
Package
144-pin HLQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* µPD70F4003/4004/4005/4006 only
Generic Name
V850E2/FK4 (Under development)
Part No.
µPD70F3555 µPD70F4007 µPD70F3556 µPD70F4008 µPD70F3557 µPD70F4009 µPD70F3558 µPD70F4010
CPU name
V850E2M
CPU performance (Dhrystone)
162 MIPS (@ 80 MHz)
Internal ROM
768 KB (ash) 1 MB (ash) 1.5 MB (ash) 2 MB (ash)
Internal RAM
64 KB 80 KB 112 KB 144 KB
Data ash
32 KB 64 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
181 185 181 185 181 185 181 185
External
17
Timer/counter
32-bit timer: 4 ch
×
2 units
16-bit timer: 16 ch
×
7 units
Watchdog timer
2 ch
Serial interface
UART (LIN compatible)
×
8 ch
CSI
×
2 ch
CSI (With FIFO)
×
3 ch
I
2
C
×
1 ch
CAN controller
×
4 ch
FlexRay controller
×
2 ch
×
1 unit*
A/D converter
12 bits
×
24 ch
×
1 unit, 12 bits
×
16 ch
×
1 unit
D/A converter
-
DMA controller
8
Ports I/O
134
Input
-
Debug control unit
Provided (RUN/break/trace)
Other peripheral functions
POC, LVI, clock monitor, comparator
×
2, random number generator, data CRC, key return: 8 ch
Operating frequency
When using main clock: 80 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.0 V to 5.5 V
Package
176-pin HLQFP (24
×
24 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* µPD70F4007/4008/4009/4010 only
Generic Name
V850E2/FL4 (Under development)
Part No.
µPD70F3559 µPD70F4011 µPD70F3560 µPD70F4012
CPU name
V850E2M
CPU performance (Dhrystone)
162 MIPS (@ 80 MHz)
Internal ROM
1.5 MB (ash) 2 MB (ash)
Internal RAM
112 KB 144 KB
Data ash
64 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
196 200 196 200
External
17
Timer/counter
32-bit timer: 4 ch
×
2 units
16-bit timer: 16 ch
×
8 units
Watchdog timer
2 ch
Serial interface
UART (LIN compatible)
×
12 ch
CSI
×
2 ch
CSI (With FIFO)
×
3 ch
I
2
C
×
1 ch
CAN controller
×
5 ch
FlexRay controller
×
2 ch
×
1 unit*
A/D converter
12 bits
×
24 ch
×
2 units
D/A converter
-
DMA controller
8
Ports I/O
164
Input
-
Debug control unit
Provided (RUN/break/trace)
Other peripheral functions
POC, LVI, clock monitor, comparator
×
2, random number generator, data CRC, key return: 8 ch
Operating frequency
When using main clock: 80 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.0 V to 5.5 V
Package
208-pin QFP (28
×
28 mm), 256-pin PBGA (21
×
21 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* µPD70F4011/4012 only
66 67
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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