Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 28
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3 V Operation 3 V Operation
Generic Name
V850ES/SJ2-H V850ES/SJ2
Part No.
Without IEBus, CAN
µPD703265HY µPD703266HY µPD70F3266HY µPD703264Y µPD70F3264Y µPD703265Y µPD703266Y µPD70F3266Y
On-chip IEBus
µPD703275HY µPD703276HY µPD70F3276HY µPD703274Y µPD70F3274Y µPD703275Y µPD703276Y µPD70F3276Y
On-chip
CAN
1 ch
µPD703285HY µPD703286HY µPD70F3286HY µPD703284Y µPD70F3284Y µPD703285Y µPD703286Y µPD70F3286Y
2 ch
µPD703287HY µPD703288HY µPD70F3288HY − − µPD703287Y µPD703288Y µPD70F3288Y
CPU name
V850ES V850ES
CPU performance (Dhrystone)
66 MIPS (@ 32 MHz) 43 MIPS (@ 20 MHz)
Internal ROM
512 KB (mask) 640 KB (mask) 640 KB (ash) 384 KB (mask) 384 KB (ash) 512 KB (mask) 640 KB (mask) 640 KB (ash)
Internal RAM
40 KB 48 KB 32 KB 40 KB 48 KB
External bus
interface
Bus type
Multiplexed/separate Multiplexed/separate
Address bus
24 bits 24 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
4 4
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
60*
1
/64*
2
/68*
3
(including one NMI for each) 61*
1
/65*
2
/69*
3
(including one NMI for each)
External
10 (10)*
4
(including one NMI) 10 (10)*
4
(including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
9 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
9 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)
×
1 ch
CSI
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)
×
1 ch
A/D converter
10 bits
×
16 ch 10 bits
×
16 ch
D/A converter
8 bits
×
2 ch 8 bits
×
2 ch
DMA controller
4 ch 4 ch
Ports I/O
128 128
Input
- -
Debug control unit
-
Provided (RUN/break)
-
Provided (RUN/break)
-
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
IEBus controller: 1 ch*
5
CAN controller: 1 ch*
6
CAN controller: 2 ch*
7
ROM correction: 4 points
Real-time output
Clock monitor, CRC
Watch timer: 1 ch
IEBus controller: 1 ch*
8
CAN controller: 1 ch*
9
CAN controller: 2 ch*
10
ROM correction: 4 points
Real-time output
LVI/clock monitor, CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
Power supply voltage
3.0 V to 3.6 V (@ 32 MHz) 2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V) (@ 20 MHz)
Package
144-pin LQFP (20
×
20mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. Products without IEBus and CAN only
*2. Products with IEBus or CAN only
*3. Products with 2 ch CAN only
*4. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*5. µPD703275HY/3276HY/F3276HY only
*6. µPD703285HY/3286HY/F3286HY only
*7. µPD703287HY/3288HY/F3288HY only
*8. µPD703274Y/F3274Y/3275Y/3276Y/F3276Y only
*9. µPD703284Y/F3284Y/3285Y/3286Y/F3286Y only
*10. µPD703287Y/3288Y/F3288Y only
*7. µPD703280Y/3281Y/F3281Y/3282Y/3283Y/F3283Y only
*8. µPD703260Y/3261Y/F3261Y/3270Y/3271Y/F3271Y only
Generic Name
V850ES/SG2-H V850ES/SG2
Part No.
Without IEBus, CAN
µPD703262HY µPD703263HY µPD70F3263HY µPD703260Y µPD703261Y µPD70F3261Y µPD703262Y µPD703263Y µPD70F3263Y
On-chip IEBus
µPD703272HY µPD703273HY µPD70F3273HY µPD703270Y µPD703271Y µPD70F3271Y µPD703272Y µPD703273Y µPD70F3273Y
On-chip CAN
µPD703282HY µPD703283HY µPD70F3283HY µPD703280Y µPD703281Y µPD70F3281Y µPD703282Y µPD703283Y µPD70F3283Y
CPU name
V850ES V850ES
CPU performance (Dhrystone)
66 MIPS (@ 32 MHz) 43 MIPS (@ 20 MHz)
Internal ROM
512 KB (mask) 640 KB (mask) 640 KB (ash) 256 KB (mask) 384 KB (mask) 384 KB (ash) 512 KB (mask) 640 KB (mask) 640 KB (ash)
Internal RAM
40 KB 48 KB 24 KB 32 KB 40 KB 48 KB
External bus
interface
Bus type
Multiplexed/separate Multiplexed/separate
Address bus
22 bits 22 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
- -
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
47*
1
/51*
2
(including one NMI for each) 48*
1
/52*
2
(Including one NMI for each)
External
9 (9)*
3
(including one NMI) 9 (9)*
3
(including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
A/D converter
10 bits
×
12 ch 10 bits
×
12 ch
D/A converter
8 bits
×
2 ch 8 bits
×
2 ch
DMA controller
4 ch 4 ch
Ports I/O
84 84
Input
- -
Debug control unit
-
Provided (RUN/break)
-
Provided (RUN/break)
-
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
IEBus controller: 1 ch*
4
CAN controller: 1 ch*
5
ROM correction: 4 points
Real-time output
Clock monitor, CRC
Watch timer: 1 ch
IEBus controller: 1 ch*
6
CAN controller: 1 ch*
7
ROM correction: 4 points
Real-time output
LVI/clock monitor, CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
Power supply voltage
3.0 V to 3.6 V (@ 32 MHz) 2.85 V to 3.6 V (A /D converter: 3.0 V to 3.6 V) (@ 20 MHz)
Package
100-pin LQFP (14
×
14mm) 100-pin LQFP (14
×
14 mm)
100-pin QFP (14
×
20 mm)*
8
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*4. µPD703272HY/3273HY/F3273HY only
*5. µPD703282HY/3283HY/F3283HY only
*6. µPD703270Y/3271Y/F3271Y/3272Y/3273Y/F3273Y only
*1. Products without IEBus and CAN only
*2. Products with IEBus or CAN only
*3. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/SG1
Part No.
µPD703249Y
CPU name
V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz)
Internal ROM
256 KB (mask)
Internal RAM
12 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
-
Memory controller
SRAM, etc.
Interrupt sources Internal
32 (including one NMI)
External
9 (9)* (including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
5 ch
Watchdog timer
1 ch
Serial interface
CSI
×
2 ch
CSI/I
2
C
×
1 ch
UART
×
2 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
12 ch
D/A converter
-
DMA controller
-
Ports I/O
84
Input
-
Debug control unit
-
Other peripheral functions
Watch timer: 1 ch, ROM correction: 4 points, clock monitor
Operating frequency
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
Power supply voltage
2.85 V to 3.6 V
(A/D converter: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm)
100-pin QFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Low-End Lineup (10/10)Low-End Lineup (9/10)
54 55
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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