Renesas Single-Chip Microcomputer M34519T-MCU Spécifications télécharger pdf (Page 9)

Product Lineup

Features

V850E2/ML4

All ash products, for general-purpose applications

512 MIPS @ 200 MHz, internal 1.1 V to 1.3 V/

external 3.0 V to 3.6 V operation

ROM/RAM: 768 KB/128 KB*, 1 MB/128 KB*

On-chip CAN (1 ch)

USB (Host, Function), Ethernet controller, and DMAC

216-pin LQFP

* Includes 64 KB of expanded internal RAM.

V850ES/SG3, SJ3

All Flash products, for car infotainment systems

69 MIPS @ 32 MHz, 2.85 to 3.6 V operation (A/D converter: 3.0 to 3.6 V)

ROM/RAM: 256 KB/24 KB to 1024 KB/60 KB

On-chip CAN (2 ch max.), LIN-compatible UART (4 ch max.), IEBus

(1 ch), multi-channel serial interface, LVI, clock monitor, CRC, DMAC,

and on-chip debugger

5 V withstand-voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

100-pin LQFP (SG3), 144-pin LQFP (SJ3)

V850E2/SG4-H,SJ4-H,SK4-H

All Flash products, for car infotainment systems

325 MIPS @ 160 MHz, internal 1.1 to 1.3 V/

external 3.0 to 3.6 V operation

ROM/RAM: 1 MB/96 KB to 2 MB/192 KB

On-chip CAN (2 ch max.), IEBus (1 ch), LVI, DMAC, on-chip debugger,

and Ethernet controller (V850E2/SK4-H only)

100-pin LQFP (SG4-H), 144-pin LQFP (SJ4-H), 176-pin LQFP (SK4-H)

V850ES/SG2, SJ2, SG2-H, SJ2-H

For car infotainment systems

43 MIPS @ 20 MHz, 2.85 to 3.6 V operation

(A/D converter: 3.0 to 3.6 V) (SG2, SJ2)

66 MIPS @ 32 MHz, 3.0 to 3.6 V operation (SG2-H, SJ2-H)

ROM/RAM: 256 KB/24 KB (SG2, SJ2 only),

384 KB/32 KB (SG2, SJ2 only), 512 KB/40 KB,

640 KB/48 KB

On-chip CAN (2 ch max.), LIN-compatible UART (4 ch max.),

multi-channel serial interface, LVI (SG2, SJ2 only), clock monitor,

CRC, DMAC, and on-chip debugger

5 V withstand-voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

100-pin LQFP (SG2, SG2-H), 144-pin LQFP (SJ2, SJ2-H)

V850ES/SG1

For car infotainment systems

43 MIPS @ 20 MHz, 2.85 to 3.6 V operation (A/D converter: 3.0 to 3.6 V)

ROM/RAM: 128 KB/8 KB

On-chip CAN (1 ch), clock monitor, and DMAC

5 V withstand-voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

100-pin LQFP

3 V operation lineup

V850E2M high-

performance CPU

FPU

Large-capacity ash ROM

V850E2M dual-core CPU

FPU

Large-capacity ash ROM

Remark See Product Specication List (pp. 73 to 79) for details about the product specications.

In mass

production

64-pin48-pin 80-pin 100-pin 144-pin

176-pin and higher

V850ES/SG2-H

32 MHz, 100-pin

V850ES/SJ2-H

32 MHz, 144-pin

V850ES/SG2

20 MHz, 100-pin

V850ES/SJ2

20 MHz, 144-pin

V850ES/SG1

20 MHz, 100-pin

V850ES/SG3

32 MHz, 100-pin

V850ES/SJ3

32 MHz, 144-pin

V850E/SK3-H

48 MHz, 176-pin

V850E/SJ3-H

48 MHz, 144-pin

V850ES/JG3-H

48 MHz, 100-pin

V850ES/JE3-H

48 MHz, 64-pin

V850ES/JC3-H

48 MHz, 48-pin

V850ES/JH3-H

48 MHz, 128-pin

V850E2M high-

performance CPU

Large-capacity ash ROM

V850E2/SG4-H

160 MHz, 100-pin

V850E2/SJ4-H

160 MHz, 144-pin

V850E2/SK4-H

160 MHz, 176-pin

V850E2/MN4

200 MHz, 304-pin

V850ES/JE3-E

50 MHz, 64-pin

V850ES/JJ3-E

50 MHz, 144-pin

V850ES/JH3-E

50 MHz, 128-pin

V850ES/JF3-E

50 MHz, 80-pin

V850ES/JG3-E

50 MHz, 100/121-pin

All ash products, for car infotainment systems

95 MIPS @ 48 MHz, 2.85 to 3.6 V operation (A/D converter: 3.0 to 3.6 V)

ROM/RAM: 512 KB/60 KB (SJ3-H only), 768 KB/76 KB* (SJ3-H only),

1024 KB/76 KB*, 1280 KB/92 KB**, 1536 KB/92 KB**

On-chip CAN (2 ch max.), UART (8 ch max. (including two UART

channels with FIFO buffers)), IEBus (1 ch), multi-channel serial

interface, LVI, clock monitor, CRC, DMAC, real-time counter,

SSCG***, and on-chip debugger

5 V withstand-voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

144-pin LQFP (SJ3-H), 176-pin LQFP (SK3-H)

* Includes 16 KB of expanded internal RAM.

** Includes 32 KB of expanded internal RAM.

*** Spread spectrum frequency synthesizer clock generator

V850E/SJ3-H, SK3-H

Under

development

V850E2/ML4

200 MHz, 216-pin

All Flash products, for general-purpose applications

103 MIPS @ 50 MHz, 2.85 to 3.6 V operation (A/D converter, USB

controller: 3.0 to 3.6 V)

ROM/RAM: 256 KB/64 KB* to 512 KB/124 KB**

CAN × 1 ch, UART supporting LIN x max 3 ch (JE3-E) to 8 ch (JJ3-E)

USB controller: USB 2.0 function (full-speed) × 1 ch

Ethernet controller × 1 ch

64-pin LQFP/WQFN (JE3-E), 64-pin FBGA (µPD70F3824),

80-pin LQFP (JF3-E), 100-pin LQFP/121-pin FBGA (JG3-E),

128-pin LQFP (JH3-E), 144-pin LQFP (JJ3-E)

* Includes 16 KB of data-only RAM.

** Includes 64 KB of data-only RAM.

V850ES/JE3-E, JF3-E, JG3-E, JH3-E, JJ3-E

Under

planning

ASSP Lineup (CAN)

All ash products, for general-purpose applications

512 MIPS @ 200 MHz, internal 1.1 to 1.3 V/

external 3.0 to 3.6 V operation

ROM/RAM: 2 MB/128 MB, 1 MB/128 KB, 1 MB/64 KB

On-chip CAN (2 ch)

USB (Host, Function), Ethernet controller, and DMAC

Ultra-high-speed dual-core CPU

304-pin FBGA

V850E2/MN4

All ash products, for general-purpose applications

98 MIPS @ 48 MHz, 2.85 to 3.6 V operation

(A/D converter, USB controller: 3.0 to 3.6 V)

ROM/RAM: 256 KB/24 KB to 256 KB/40 KB*

On-chip CAN (1 ch) and LIN-compatible UART (4 ch or 5 ch max.)

USB controller: USB 2.0 function (full-speed) × 1 ch

48-pin LQFP/WQFN (JC3-H), 64-pin LQFP/FBGA/WQFN (JE3-H),

100-pin LQFP (JG3-H), 128-pin LQFP (JH3-H)

* Includes 8 KB of data-only RAM.

V850ES/JC3-H, JE3-H, JG3-H, JH3-H

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Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 9

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