Renesas Single-Chip Microcomputer M34519T-MCU Spécifications télécharger pdf (Page 5)

Product Lineup

Low-End Lineup

Features

3 V opration

All Flash lineup

5 V opration

All Flash lineup

Sxx lineup

ROMless

Internal RAM: 48 KB

V850ES/JG3, JJ3

All Flash products

69 MIPS @ 32 MHz, 2.85 to 3.6 V operation (A/D converter: 3.0 to 3.6 V)

ROM/RAM: 384 KB/32 KB, 512 KB/40 KB, 768 KB/60 KB, 1024 KB/60 KB

On-chip multi-channel serial interface, LVI, clock monitor, DMAC,

and on-chip debugger

5 V withstand voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

100-pin LQFP (JG3), 144-pin LQFP (JJ3)

V850ES/SG2-H, SJ2-H

66 MIPS @ 32 MHz, 3.0 to 3.6 V operation

ROM/RAM: 512 KB/40 KB, 640 KB/48 KB

On-chip multi-channel serial interface, clock monitor, CRC, DMAC,

and on-chip debugger

5 V withstand voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

100-pin LQFP (SG2-H), 144-pin LQFP (SJ2-H)

V850ES/ST2

ROMless product with large-capacity RAM

34 MHz, 3.0 to 3.6 V operation

ROM/RAM: ROMless/48 KB

120-pin TQFP/144-pin LQFP

V850ES/SG2, SJ2

43 MIPS @ 20 MHz, 2.85 to 3.6 V operation (A/D converter: 3.0 to 3.6 V)

ROM/RAM: 256 KB/24 KB, 384 KB/32 KB, 512 KB/40 KB, 640 KB/48 KB

On-chip multi-channel serial interface, LVI, clock monitor, CRC,

DMAC, and on-chip debugger

5 V withstand voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

100-pin LQFP (SG2), 100-pin QFP (SG2 (ROM: 256 KB/384 KB

versions only)), 144-pin LQFP (SJ2)

V850ES/SG1

Part of V850ES/SG2 lineup

43 MIPS @ 20 MHz, 2.85 to 3.6 V operation (A/D converter: 3.0 to 3.6 V)

ROM/RAM: 256 KB/12 KB

On-chip clock monitor

5 V withstand voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

100-pin LQFP/100-pin QFP

V850ES/SG1

20 MHz, 100-pin

V850ES/SG2

20 MHz, 100-pin

V850ES/SJ2

20 MHz, 144-pin

V850ES/SG2-H

32 MHz, 100-pin

V850ES/SJ2-H

32 MHz, 144-pin

V850ES/ST2

34 MHz, 120/144-pin

V850ES/JG3

32 MHz, 100-pin

V850ES/JJ3

32 MHz, 144-pin

V850ES/JG3-E

50 MHz, 100/121-pin

V850ES/JF3-E

50 MHz, 80-pin

V850ES/JE3-E

50 MHz, 64-pin

V850ES/JJ3-E

50 MHz, 144-pin

V850ES/JH3-E

50 MHz, 128-pin

V850ES/H F3

32 MHz, 80-pin

V85 0E S/H E3

32 MHz, 64-pin

V850ES/HJ3

32 MHz, 144-pin

V850ES/HG3

32 MHz, 100-pin

V850ES/J G3-U

48 MHz, 100-pin

V850ES/JH3-U

48 MHz, 128-pin

V850ES/JG3-L

20 MHz, 100/121-pin

V850ES/JF3- L

20 MHz, 80-pin

V850ES/JC3-L

20 MHz, 40/48-pin

V850ES/JE3-L

20 MHz, 64-pin

V850ES/J C3-H

48 MHz, 40/48-pin

V850ES/JG3-H

48 MHz, 100-pin

V850ES/JH3-H

48 MHz, 128-pin

V850ES/JE3-H

48 MHz, 64-pin

V850ES/JC3-L, JE3-L, JF3-L, JG3-L

All Flash products

43 MIPS @ 20 MHz, 2.0 to 3.6 V operation (JG3-L*),

2.2 to 3.6 V operation (JC3-L, JE3-L, JF3-L)

ROM/RAM: 16 KB/8 KB, 1024 KB/80 KB

Low power operation 36 mW (3.0 V, 20 MHz)

Function and pin compatibility with V850ES/Jx3 and can use

V850ES/Jx3 development environment

5 V withstand voltage ports incorporated, and 5 V output is possible

by setting N-ch open-drain output

40-pin WQFN (JC3-L), 48-pin LQFP/WQFN (JC3-L), 64-pin LQFP/FBGA/WQFN

(JE3-L), 80-pin LQFP (JF3-L), 100-pin LQFP/121-pin FBGA (JG3-L)

* 2.2 V to 3.6 V operation for µPD70F3737 and µPD70F3738

V850ES/JC3-H, JE3-H, JG3-H, JH3-H, JG3-U, JH3-U

All Flash products

98 MIPS @ 48 MHz, 2.85 to 3.6 V operation

(A/D converter, USB controller: 3.0 to 3.6 V)

ROM/RAM: 16 KB/8 KB to 512 KB/56 KB*

USB controller: USB 2.0 function (full-speed) × 1 ch,

USB 2.0 host (full-speed) × 1 ch (JG3-U, JH3-U only)

40-pin WQFN (JC3-H), 48-pin LQFP/WQFN (JC3-H), 64-pin

LQFP/WQFN (JE3-H), 64-pin FBGA (µPD70F3824), 100-pin LQFP

(JG3-H, JG3-U), 128-pin LQFP (JH3-H, JH3-U)

* Includes 8 KB of data-only RAM.

Remark See Product Specication List (pp. 46 to 55) for details about the product specications.

In mass

production

Some models in

mass production

Under

development

64-pin40/48-pin 80-pin 100-pin 128-pin

144-pin and higher

V850ES/HE3, HF3, HG3, HJ3

All Flash products

69 MIPS @ 32 MHz, 66 MIPS @ 32 MHz (µPD70F3757 only),

3.7 to 5.5 V operation (A/D converter: 4.0 to 5.5 V)

ROM/RAM: 128 KB/8 KB to 512 KB/32 KB

On-chip multi-channel A/D converter, POC, LVI, DMAC,

on-chip debugger, 3-phase inverter control, and SSCG*

64-pin LQFP (HE3), 80-pin LQFP (HF3), 100-pin LQFP (HG3),

144-pin LQFP (HJ3)

* Spread spectrum frequency synthesizer clock generator

V850ES/JE3-E, JF3-E, JG3-E, JH3-E, JJ3-E

All Flash products

103 MIPS @ 50 MHz, 2.85 to 3.6 V operation

(A/D converter, USB controller: 3.0 to 3.6 V)

ROM/RAM: 64 KB/32 KB* to 512 KB/124 KB**

USB controller: USB 2.0 function (full-speed) × 1 ch,

Ethernet controller × 1 ch

64-pin WQFN (JE3-E), 80-pin LQFP (JF3-E), 100-pin LQFP/121-pin

FBGA (JG3-E), 128-pin LQFP (JH3-E), 144-pin LQFP (JJ3-E)

* Includes 16 KB of data-only RAM.

** Includes 64 KB of data-only RAM.

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Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 5

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