Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 24
- Page / 51
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Generic Name
V850ES/HE3 V850ES/HF3
Part No.
µPD70F3747 µPD70F3750
CPU name
V850ES V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz) 69 MIPS (@ 32 MHz)
Internal ROM
128 KB (ash) 256 KB (ash)
Internal RAM
8 KB 16 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
43 (including one NMI) 43 (including one NMI)
External
9 (9)* (including one NMI) 9 (9)* (including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
1 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
1 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
10 ch 10 bits
×
12 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
51 67
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
3-phase inverter control, watch timer:1 ch, POC/LVI/clock monitor, RAM retention ag, SSCG 3-phase inverter control, watch timer: 1 ch, POC/LVI/clock monitor, RAM retention ag, SSCG
Operating frequency
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
64-pin LQFP (10
×
10 mm) 80-pin LQFP (12
×
12 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/HG3 V850ES/HJ3
Part No.
µPD70F3752 µPD70F3755 µPD70F3757
CPU name
V850ES V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz) 69 MIPS (@ 32 MHz) 66 MIPS (@ 32 MHz)
Internal ROM
256 KB (ash) 256 KB (ash) 512 KB (ash)
Internal RAM
16 KB 16 KB 32 KB
External bus
interface
Bus type
-
Multiplexed
Address bus
-
16-bit
Data bus
-
8/16-bit
Chip select signal
-
4
Memory controller
-
SRAM, etc.
Interrupt sources Internal
51 (including one NMI) 58 (including one NMI) 64 (including one NMI)
External
12 (12)*
1
(including one NMI) 16 (16)*
1
(including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
3 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
3 ch
I
2
C
×
1 ch
CSI
×
3 ch
UART (LIN compatible)
×
3 ch
I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)
×
4 ch
UART (LIN compatible)/CSI
×
2 ch*
2
UART (LIN compatible)/I
2
C
×
1 ch
A/D converter
10 bits
×
16 ch 10 bits
×
24 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
84 128
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
3-phase inverter control, watch timer: 1 ch, POC/LVI/clock monitor, RAM retention ag, SSCG
3-phase inverter control, watch timer: 1 ch, POC/LVI/clock monitor, RAM retention ag, SSCG
Operating frequency
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
100-pin LQFP (14
×
14 mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*2. Two channels identical to independent UART are available. The V850ES/HJ3 has a total of 6 UART channels.
Low-End Lineup (2/10)Low-End Lineup (1/10)
5 V Operation 3 V Operation
Generic Name
V850ES/JE3-E (Under development) V850ES/JF3-E (Under development)
Part No.
µPD70F3826 µPD70F3827 µPD70F3828 µPD70F3829 µPD70F3830 µPD70F3831 µPD70F3832 µPD70F3833
CPU name
V850ES V850ES
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz) 103 MIPS (@ 50 MHz)
Internal ROM
64 KB (ash) 128 KB (ash) 256 KB (ash) 64 KB (ash) 128 KB (ash) 256 KB (ash)
Internal RAM
32 KB*
1
48 KB*
1
64 KB*
1
32 KB*
1
48 KB*
1
64 KB*
1
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
62 (Including one NMI) 66 (Including one NMI) 66 (Including one NMI)
67 (Including one NMI)
External
11 (11)*
2
(Including one NMI) 20 (20)*
2
(Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch
Serial interface
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
2 ch
CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
2 ch
CSI
×
2 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
8 ch 10 bits
×
8 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
29 41
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch USB 2.0 function (full-speed)
×
1 ch
Ethernet controller
1 ch 1 ch
Other peripheral functions
Real-time counter (RTC), LVI/clock monitor, CRC, RAM retention ag Motor control, real-time counter (RTC), LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
64-pin LQFP (10
×
10 mm), 64-pin WQFN (9
×
9 mm) 80-pin LQFP (12
×
12 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. Includes 16 KB of data-only RAM.
*2. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JG3-E (Under development)
Part No.
µPD70F3834 µPD70F3835 µPD70F3836 µPD70F3837
CPU name
V850ES
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz)
Internal ROM
64 KB (ash) 128 KB (ash) 256 KB (ash)
Internal RAM
32 KB*
1
48 KB*
1
64 KB*
1
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
66 (Including one NMI) 70 (Including one NMI)
External
22 (22)*
2
(Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch
Serial interface
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
2 ch
CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
2 ch
CSI
×
2 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
10 ch
D/A converter
-
DMA controller
4 ch
Ports I/O
64
Input
-
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
Ethernet controller
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm), 121-pin FBGA (8
×
8 mm)*
3
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. Includes 16 KB of data-only RAM.
*2. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*3. µPD70F3837 only
46 47
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
Produits connexes et manuels pour Mise en réseau Renesas Single-Chip Microcomputer M34519T-MCU
(63 pages)
(46 pages)© 2020, manymanuals.fr. Tous droits réservés | 0.057 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels