Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 30
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ASSP Lineup (Inverter Control, etc.) (1/5) ASSP Lineup (Inverter Control, etc.) (2/5)
Generic Name
V850E/IG4 V850E/IH4
Part No.
µPD70F3913 µPD70F3914 µPD70F3915 µPD70F3916 µPD70F3917 µPD70F3918
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
197 MIPS (@ 100 MHz) 197 MIPS (@ 100 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 480 KB (ash) 256 KB (ash) 384 KB (ash) 480 KB (ash)
Internal RAM
24 KB 24 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
82 (Including one NMI) 82 (Including one NMI)
External
22 (22)* 22 (22)*
Timer/counter
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TAA)
×
1 ch
16-bit timer/event counter (TMT)
×
4 ch (encoder count function: 2 ch)
16-bit timer/counter (TAA)
×
2 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TAA)
×
1 ch
16-bit timer/event counter (TMT)
×
4 ch (encoder count function: 2 ch)
16-bit timer/counter (TAA)
×
2 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI/UART (With FIFO)
×
1 ch
CSI/UART
×
2 ch
UART/I
2
C
×
1 ch
CSI/UART (With FIFO)
×
1 ch
CSI/UART
×
2 ch
UART/I
2
C
×
1 ch
A/D converter
12 bits
×
4 ch (A /D converter 0), 12 bits
×
3 ch (A /D converter 1) (conversion time: 2 µs)
10 bits
×
12 ch
12 bits
×
4 ch, 2 units (conversion time: 2 µs)
10 bits
×
12 ch
D/A converter
- -
DMA controller
7 ch 7 ch
Ports I/O
55 68
Input
12 12
Debug control unit
Provided (RUN/break) Provided (RUN/break/trace)
USB controller
- -
Other peripheral functions
3-phase inverter control, 6 operational ampliers, comparators: 12 circuits,
software pull-up, POC/LVI/clock monitor
3-phase inverter control, 6 operational ampliers, comparators: 12 circuits,
software pull-up, POC/LVI/clock monitor
Operating frequency
10 to 100 MHz 10 to 100 MHz
Power supply voltage
1.5 V/5.0 V 1.5 V/5.0 V
Package
100-pin LQFP (14
×
14 mm)
100-pin LQFP (14
×
20 mm)
128-pin LQFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850E/IG4-H V850E/IH4-H
Part No.
µPD70F3919 µPD70F3920 µPD70F3921 µPD70F3922 µPD70F3923 µPD70F3924
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
197 MIPS (@ 100 MHz) 197 MIPS (@ 100 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 480 KB (ash) 256 KB (ash) 384 KB (ash) 480 KB (ash)
Internal RAM
24 KB 24 KB
External bus
interface
Bus type
Multiplexed Multiplexed/separate
Address bus
16 bits Multiplexed: 16 bits, separate: 8 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
2 2
Memory controller
SRAM, etc. (5 V interface) SRAM, etc.
Interrupt sources Internal
84 (Including one NMI) 84 (Including one NMI)
External
22 (22)* 22 (22)*
Timer/counter
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TAA)
×
1 ch
16-bit timer/event counter (TMT)
×
4 ch (encoder count function: 2 ch)
16-bit timer/counter (TAA)
×
2 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TAA)
×
1 ch
16-bit timer/event counter (TMT)
×
4 ch (encoder count function: 2 ch)
16-bit timer/counter (TAA)
×
2 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI/UART (With FIFO)
×
1 ch
CSI/UART
×
2 ch
UART/I
2
C
×
1 ch
CSI/UART (With FIFO)
×
1 ch
CSI/UART
×
2 ch
UART/I
2
C
×
1 ch
A/D converter
12 bits
×
4 ch (A /D converter 0), 12 bits
×
3 ch (A /D converter 1) (conversion time: 2 µs)
10 bits
×
12 ch
12 bits
×
4 ch, 2 units (conversion time: 2 µs)
10 bits
×
12 ch
D/A converter
- -
DMA controller
7 ch 7 ch
Ports I/O
51 68
Input
12 12
Debug control unit
Provided (RUN/break) Provided (RUN/break/trace)
USB controller
USB 2.0 function (full-speed)
×
1 ch USB 2.0 function (full-speed)
×
1 ch
Other peripheral functions
3-phase inverter control, 6 operational ampliers, comparators: 12 circuits,
software pull-up, POC/LVI/clock monitor
3-phase inverter control, 6 operational ampliers, comparators: 12 circuits,
software pull-up, POC/LVI/clock monitor
Operating frequency
10 to 100 MHz 10 to 100 MHz
Power supply voltage
1.5 V (internal)/5.0 V (pin, A/D)/3.3 V (USB) 1.5 V (internal)/5.0 V (A/D)/3.3 V (pin, USB)
Package
100-pin LQFP (14
×
14 mm) 128-pin LQFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850E/IG3 V850E/IF3
Part No.
µPD70F3453 µPD70F3454 µPD70F3451 µPD70F3452
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
131 MIPS (@ 64 MHz) 131 MIPS (@ 64 MHz)
Internal ROM
128 KB (ash) 256 KB (ash) 128 KB (ash) 256 KB (ash)
Internal RAM
8 KB 12 KB 8 KB 12 KB
External bus
interface
Bus type
-
Multiplexed/separate *
1
-
Address bus
-
Multiplexed: 16 bits, separate: 8 bits*
1
-
Data bus
-
8/16 bits*
1
-
Chip select signal
-
2*
1
-
Memory controller
-
SRAM, etc.*
1
-
Interrupt sources Internal
75 (including one NMI) 74 (including one NMI)
External
21 (18)*
2
15 (12)*
2
Timer/counter
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TAA)
×
3 ch
16-bit timer/event counter (TMT)
×
2 ch (encoder count function: 2 ch)
16-bit timer/counter (TAA)
×
2 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TAA)
×
3 ch
16-bit timer/event counter (TMT)
×
2 ch (encoder count function: 1 ch)
16-bit timer/counter (TAA)
×
2 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI/UART (with FIFO)
×
1 ch
CSI/UART
×
2 ch
UART/I
2
C
×
1 ch
CSI/UART (with FIFO)
×
1 ch
CSI/UART
×
2 ch
UART/I
2
C
×
1 ch
A/D converter
12 bits
×
5 ch, 2 units (conversion time: 2 µs)
10 bits
×
8 ch
12 bits
×
5 ch, 2 units (conversion time: 2 µs)
10 bits
×
4 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
56 44
Input
8 4
Debug control unit
Provided (RUN/break)
-
Other peripheral functions
3-phase inverter control, 4 operational ampliers, comparators: 8 circuits,
software pull-up, POC/LVI/clock monitor
3-phase inverter control, 4 operational ampliers, comparator: 8 circuits,
software pull-up, POC/LVI/clock monitor
Operating frequency
4 to 64 MHz 4 to 64 MHz
Power supply voltage
3.5 V to 5.5 V
(A/D converter: 4.0 V to 5.5 V)
3.5 V to 5.5 V
(A/D converter: 4.0 V to 5.5 V)
Package
100-pin LQFP (14
×
14 mm)
100-pin LQFP (14
×
20 mm)
161-pin FBGA (10
×
10 mm)*
3
80-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. µPD70F3454GC-8EA-A only *2. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode. *3. µPD70F3454F1-DA9-A only
Generic Name
V850E/MA3
Part No.
µPD703131BY µPD703132BY µPD703133BY µPD703134BY µPD70F3134BY µPD703136BY
CPU name
V850E1
CPU performance (Dhrystone)
158 MIPS (@ 80 MHz)
Internal ROM
256 KB (mask) 512 KB (mask) 512 KB (ash) 256 KB (mask)
Internal RAM
16 KB 32 KB 16 KB 32 KB 8 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
26 bits
Data bus
8/16 bits
Chip select signal
8
Memory controller
SDRAM, SRAM, etc.
Interrupt sources Internal
41 (including one NMI)
External
26 (26)* (including one NMI)
Timer/counter
16-bit interval timer (TMD)
×
4 ch
16-bit timer/event counter (TMP)
×
3 ch
16-bit timer/event counter (TMQ)
×
1 ch (3-phase inverter control PWM timer compatible)
16-bit encoder counter/timer (TMENC)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI/UART
×
3 ch
UART/I
2
C
×
1 ch
A/D converter
10 bits
×
8 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
101
Input
11
Debug control unit
Provided (RUN/break)
Other peripheral functions
3-phase inverter control, ROM correction: 4 points
Operating frequency
5 to 80 MHz
Power supply voltage
2.3 V to 2.7 V (internal)/3.0 V to 3.6 V (external)
Package
144-pin LQFP (20
×
20 mm)
161-pin FBGA (13
×
13 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
58 59
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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