
3 V Operation 3 V Operation
Generic Name
V850ES/JG3-H
Part No.
µPD70F3760 µPD70F3761 µPD70F3762 µPD70F3770
CPU name
V850ES
CPU performance (Dhrystone)
98 MIPS (@ 48 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 512 KB (ash) 256 KB (ash)
Internal RAM
40 KB*
1
48 KB*
1
56 KB*
1
40 KB*
1
External bus
interface
Bus type
Multiplexed
Address bus
16 bits
Data bus
8/16 bits
Chip select signal
3
Memory controller
SRAM, etc.
Interrupt sources Internal
69 (including one NMI) 73 (including one NMI)
External
17 (17)*
2
(including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
12 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
77
Input
-
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. Includes 8 KB of data-only RAM.
*2. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JH3-H
Part No.
µPD70F3765 µPD70F3766 µPD70F3767 µPD70F3771
CPU name
V850ES
CPU performance (Dhrystone)
98 MIPS (@ 48 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 512 KB (ash) 256 KB (ash)
Internal RAM
40 KB*
1
48 KB*
1
56 KB*
1
40 KB*
1
External bus
interface
Bus type
Multiplexed/separate
Address bus
24 bits
Data bus
8/16 bits
Chip select signal
3
Memory controller
SRAM, etc.
Interrupt sources Internal
69 (including one NMI) 73 (including one NMI)
External
20 (20)*
2
(including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
12 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
96
Input
-
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
128-pin LQFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. Includes 8 KB of data-only RAM.
*2 The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JG3-U V850ES/JH3-U
Part No.
µPD70F3763 µPD70F3764 µPD70F3768 µPD70F3769
CPU name
V850ES V850ES
CPU performance (Dhrystone)
98 MIPS (@ 48 MHz) 98 MIPS (@ 48 MHz)
Internal ROM
384 KB (ash) 512 KB (ash) 384 KB (ash) 512 KB (ash)
Internal RAM
48 KB*
1
56 KB*
1
48 KB*
1
56 KB*
1
External bus
interface
Bus type
Multiplexed Multiplexed/separate
Address bus
16 bits 24 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
3 3
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
72 (including one NMI) 72 (including one NMI)
External
15 (15)*
2
(including one NMI) 20 (20)*
2
(including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
A/D converter
10 bits
×
12 ch 10 bits
×
12 ch
D/A converter
8 bits
×
2 ch 8 bits
×
2 ch
DMA controller
4 ch 4 ch
Ports I/O
75 96
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
USB 2.0 host (full-speed)
×
1 ch
USB 2.0 function (full-speed)
×
1 ch
USB 2.0 host (full-speed)
×
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm) 128-pin LQFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. Includes 8 KB of data-only RAM.
*2. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JC3-L
Part No.
µPD70F3797 µPD70F3798 µPD70F3799 µPD70F3800 µPD70F3838 µPD70F3801 µPD70F3802 µPD70F3803 µPD70F3804 µPD70F3839
CPU name
V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz)
Internal ROM
16 KB (ash) 32 KB (ash) 64 KB (ash) 128 KB (ash) 256 KB (ash) 16 KB (ash) 32 KB (ash) 64 KB (ash) 128 KB (ash) 256 KB (ash)
Internal RAM
8 KB 16 KB 8 KB 16 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
43 (Including one NMI) 47 (Including one NMI)
External
6 (6)* (Including one NMI)
Timer/counter
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI
×
1 ch
UART (LIN compatible)
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
A/D converter
10 bits
×
5 ch 10 bits
×
6 ch
D/A converter
-
8 bits
×
1 ch
DMA controller
4 ch
Ports I/O
27 34
Input
-
Debug control unit
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch, real-time output, LVI/clock monitor, CRC
Operating frequency
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.2 V to 3.6 V (A/D converter: 2.7 V to 3.6 V)
Package
40-pin WQFN (6
×
6 mm) 48-pin LQFP (7
×
7 mm), 48-pin WQFN (7
×
7 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Low-End Lineup (6/10)Low-End Lineup (5/10)
50 51
Commentaires sur ces manuels