Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 31
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Noté. / 5. Basé sur avis des utilisateurs
ASSP Lineup (Inverter Control, etc.) (3/5) ASSP Lineup (Inverter Control, etc.) (4/5)
Generic Name
V850E/IA1 V850E/IA2
Part No.
µPD703116 µPD70F3116 µPD703114 µPD70F3114
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz) 82 MIPS (@ 40 MHz)
Internal ROM
256 KB (mask) 256 KB (ash) 128 KB (mask) 128 KB (ash)
Internal RAM
10 KB 6 KB
External bus
interface
Bus type
Multiplexed Multiplexed
Address bus
24 bits 22 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
8
-
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
45 42
External
20 (14)* (including one NMI) 16 (12)* (including one NMI)
Timer/counter
16-bit 3-phase inverter control PWM timer
×
2 ch
16-bit encoder counter/timer
×
2 ch
16-bit timer/counter
×
2 ch
16-bit timer/event counter
×
1 ch
16-bit interval timer
×
1 ch
16-bit 3-phase inverter control PWM timer
×
2 ch
16-bit encoder counter/timer
×
1 ch
16-bit timer/counter
×
2 ch
16-bit timer/event counter
×
1 ch
16-bit interval timer
×
1 ch
Watchdog timer
- -
Serial interface
CSI
×
2 ch
UART
×
3 ch
CSI
×
1 ch
CSI/UART
×
1 ch
UART
×
1 ch
A/D converter
10 bits
×
8 ch, 2 units 10 bits
×
6 ch (A /D converter 0)
10 bits
×
8 ch (A /D converter 1)
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
75 47
Input
8 6
Debug control unit
- -
Other peripheral functions
CAN controller
×
1 ch
-
Operating frequency
4 to 50 MHz 4 to 40 MHz
Power supply voltage
3.0 V to 3.6 V (internal)
4.5 V to 5.5 V (external)
4.5 V to 5.5 V (when internal regulator used)
Package
144-pin LQFP (20
×
20 mm) 100-pin QFP (14
×
20 mm)
100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C (110
°
C version available)
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850E/IA4 V850E/IA3
Part No.
µPD703185 µPD703186 µPD70F3186 µPD703183 µPD70F3184
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
126 MIPS (@ 64 MHz) 126 MIPS (@ 64 MHz)
Internal ROM
128 KB (mask) 256 KB (mask) 256 KB (ash) 128 KB (mask) 256 KB (ash)
Internal RAM
6 KB 12 KB 6 KB 12 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
53 (including one NMI) 49 (including one NMI)
External
8 (7)* 7 (6)*
Timer/counter
16-bit timer/event counter (TMQ)
×
2 ch (3-phase inverter control PWM timer compatible)
16-bit encoder counter/timer (TMENC)
×
2 ch
16-bit timer/event counter (TMP)
×
2 ch
16-bit timer/counter (TMP)
×
2 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMQ)
×
1 ch (3-phase inverter control PWM timer compatible)
16-bit encoder counter/timer (TMENC)
×
1 ch
16-bit timer/event counter (TMP)
×
2 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit timer/counter (TMP)
×
2 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
1 ch
UART
×
1 ch
CSI/UART
×
1 ch
CSI
×
1 ch
UART
×
1 ch
CSI/UART
×
1 ch
A/D converter
10 bits
×
4 ch, 2 units (conversion time: 2 µs)
8/10 bits
×
8 ch
10 bits
×
4 ch, 10 bits
×
2 ch (conversion time: 2 µs)
8/10 bits
×
6 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
56 44
Input
8 6
Debug control unit
-
Provided (RUN/break)
-
Other peripheral functions
3-phase inverter control, ROM correction: 4 points, operational ampliers: 6 circuits,
comparators: 6 circuits, software pull-up
3-phase inverter control, ROM correction: 4 points, operational ampliers: 5 circuits,
comparators: 5 circuits, software pull-up
Operating frequency
4 to 64 MHz 4 to 64 MHz
Power supply voltage
2.3 V to 2.7 V (internal)/4.0 V to 5.5 V (external)
(A/D converter: 4.5 V to 5.5 V)
2.3 V to 2.7 V (internal)/4.0 V to 5.5 V (external)
(A/D converter: 4.5 V to 5.5 V)
Package
100-pin LQFP (14
×
14 mm)
100-pin QFP (14
×
20 mm)
80-pin QFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/HG3 V850ES/HJ3
Part No.
µPD70F3752 µPD70F3755 µPD70F3757
CPU name
V850ES V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz) 69 MIPS (@ 32 MHz) 66 MIPS (@ 32 MHz)
Internal ROM
256 KB (ash) 256 KB (ash) 512 KB (ash)
Internal RAM
16 KB 16 KB 32 KB
External bus
interface
Bus type
-
Multiplexed
Address bus
-
16 bits
Data bus
-
8/16 bits
Chip select signal
-
4
Memory controller
-
SRAM, etc.
Interrupt sources Internal
51 (including one NMI) 58 (including one NMI) 64 (including one NMI)
External
12 (12)*
1
(including one NMI) 16 (16)*
1
(including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
2 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
3 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
3 ch
I
2
C
×
1 ch
CSI
×
3 ch
UART (LIN compatible)
×
3 ch
I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)
×
4 ch
UART (LIN compatible)/CSI
×
2 ch*
2
UART (LIN compatible)/I
2
C
×
1 ch
A/D converter
10 bits
×
16 ch 10 bits
×
24 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
84 128
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
3-phase inverter control, watch timer: 1 ch,
POC/LVI/clock monitor, RAM retention ag, SSCG
3-phase inverter control, watch timer: 1 ch,
POC/LVI/clock monitor, RAM retention ag, SSCG
Operating frequency
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
100-pin LQFP (14
×
14 mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*2. Two channels identical to independent UART are available. The V850ES/HJ3 has a total of 6 UART channels.
Generic Name
V850ES/HE3 V850ES/HF3
Part No.
µPD70F3747 µPD70F3750
CPU name
V850ES V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz) 69 MIPS (@ 32 MHz)
Internal ROM
128 KB (ash) 256 KB (ash)
Internal RAM
8 KB 16 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
43 (including one NMI) 43 (including one NMI)
External
9 (9)* (including one NMI) 9 (9)* (including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
1 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit timer/event counter (TAB)
×
1 ch
(3-phase inverter control PWM timer compatible)
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
10 ch 10 bits
×
12 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
51 67
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
3-phase inverter control, watch timer: 1 ch, POC/LVI/clock monitor, RAM retention ag, SSCG 3-phase inverter control, watch timer: 1 ch, POC/LVI/clock monitor, RAM retention ag, SSCG
Operating frequency
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.7 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
64-pin LQFP (10
×
10 mm) 80-pin LQFP (12
×
12 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
60 61
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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