Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 39
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Noté. / 5. Basé sur avis des utilisateurs
ASSP Lineup (CAN) (5/7)ASSP Lineup (CAN) (4/7)
Generic Name
V850ES/JG3-H V850ES/JH3-H
Part No.
µPD70F3770 µPD70F3771
CPU name
V850ES V850ES
CPU performance (Dhrystone)
98 MIPS (@ 48 MHz) 98 MIPS (@ 48 MHz)
Internal ROM
256 KB (ash) 256 KB (ash)
Internal RAM
40 KB*
1
40 KB*
1
External bus
interface
Bus type
Multiplexed Multiplexed/separate
Address bus
16 bits 24 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
3 3
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
73 (including one NMI) 73 (including one NMI)
External
17 (17)*
2
(including one NMI) 20 (20)*
2
(including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
CSI
×
2 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
12 ch 10 bits
×
12 ch
D/A converter
8 bits
×
2 ch 8 bits
×
2 ch
DMA controller
4 ch 4 ch
Ports I/O
77 96
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch USB 2.0 function (full-speed)
×
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor,
CRC, RAM retention ag
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor,
CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm) 128-pin LQFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. Includes 8 KB of data-only RAM.
*2. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/SG3
Part No.
µPD70F3335 µPD70F3336 µPD70F3350 µPD70F3351 µPD70F3352 µPD70F3353
CPU name
V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 512 KB (ash) 640 KB (ash) 768 KB (ash) 1024 KB (ash)
Internal RAM
24 KB 32 KB 40 KB 48 KB 60 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
-
Memory controller
SRAM, etc.
Interrupt sources Internal
52 (including one NMI)
External
9 (9)* (including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
A/D converter
10 bits
×
12 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
84
Input
-
Debug control unit
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
IEBus controller/CAN controller: 1 ch
ROM correction: 4 points
Real-time output
LVI/clock monitor/CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/SJ3
Part No.
On-chip CAN (1 ch max.)
µPD70F3354 µPD70F3355 µPD70F3356 µPD70F3357 µPD70F3358
On-chip CAN (2 ch max.)
µPD70F3364 µPD70F3365 µPD70F3366 µPD70F3367 µPD70F3368
CPU name
V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz)
Internal ROM
384 KB (ash) 512 KB (ash) 640 KB (ash) 768 KB (ash) 1024 KB (ash)
Internal RAM
32 KB 40 KB 48 KB 60 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
24 bits
Data bus
8/16 bits
Chip select signal
4
Memory controller
SRAM, etc.
Interrupt sources Internal
65*
1
/69*
2
(including one NMI for each)
External
10 (10)*
3
(including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
9 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)
×
1 ch
A/D converter
10 bits
×
16 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
128
Input
-
Debug control unit
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
IEBus controller/CAN controller*
4
: 1 ch
CAN controller: 2 ch*
5
ROM correction: 4 points
Real-time output
LVI/clock monitor/CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V)
Package
144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. Product with 1 ch CAN only
*2. Products with 2 ch CAN only
*3. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*4. µPD70F3354/F3355/F3356/F3357/F3358 only
*5. µPD70F3364/F3365/F3366/F3367/F3368 only
Generic Name
V850E/SJ3-H
Part No.
On-chip CAN (1 ch max.)
µPD70F3475A µPD70F3478A µPD70F3935A µPD70F3938A
On-chip CAN (2 ch max.)
µPD70F3476A µPD70F3479A µPD70F3936A µPD70F3939A
CPU name
V850E1
CPU performance (Dhrystone)
95 MIPS (@ 48 MHz)
Internal ROM
1280 KB (ash) 1536 KB (ash) 768 KB (ash) 1024 KB (ash)
Internal RAM
92 KB (internal RAM: 60 KB, expanded internal RAM: 32 KB) 76 KB (internal RAM: 60 KB, expanded internal RAM: 16 KB)
External bus
interface
Bus type
Multiplexed/separate
Address bus
24 bits
Data bus
8/16 bits
Chip select signal
3
Memory controller
SRAM, etc.
Interrupt sources Internal
99*
1
/103*
2
(including one NMI for each)
External
11 (11)*
3
(including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
3 ch
16-bit timer/event counter (TMP)
×
9 ch (encoder count function: 2 ch)
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch
Serial interface
UART/CSI
×
1 ch, UART/I
2
C
×
2 ch, UART/CSI/I
2
C
×
1 ch, UART/CSI (FIFO compatible)
×
1 ch,
CSI/I
2
C
×
1 ch, UART
×
1 ch, UART (FIFO compatible)
×
2 ch, CSI
×
3 ch, CSI (FIFO compatible)
×
1 ch, I
2
C
×
2 ch
or
UART/CSI
×
1 ch, UART/I
2
C
×
1 ch, UART/CSI/I
2
C
×
2 ch, UART/CSI (FIFO compatible)
×
1 ch,
CSI/I
2
C
×
1 ch, UART
×
1 ch, UART (FIFO compatible)
×
2 ch, CSI
×
2 ch, CSI (FIFO compatible)
×
1 ch, I
2
C
×
2 ch
A/D converter
10 bits
×
16 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
128
Input
-
Debug control unit
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
Real-time counter (Watch timer): 1 ch
IEBus controller/CAN controller*
4
: 1 ch
CAN controller: 2 ch*
5
ROM correction: 8 points
Real-time output
LVI/clock monitor/CRC, SSCG
Operating frequency
When using main clock: 48 MHz (max.)
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, D/A converter: 3.0 V to 3.6 V)
Package
144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. Products with 1 ch CAN only
*2. Products with 2 ch CAN only
*3. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*4. µPD70F3475, 70F3478, 70F3935, 70F3938
*5. µPD70F3476, 70F3479, 70F3936, 70F3939
76 77
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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