Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 40
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ASSP Lineup (CAN) (7/7)ASSP Lineup (CAN) (6/7)
Generic Name
V850E/SJ3-H V850E/SK3-H
Part No.
On-chip CAN (1 ch max.)
µPD70F3932A µPD70F3481A µPD70F3487A µPD70F3926A
On-chip CAN (2 ch max.)
µPD70F3933A µPD70F3482A µPD70F3488A µPD70F3927A
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
95 MIPS (@ 48 MHz) 95 MIPS (@ 48 MHz)
Internal ROM
512 KB (ash) 1536 KB (ash) 1280 KB (ash) 1024 KB (ash)
Internal RAM
60 KB (internal RAM: 60 KB, expanded internal RAM: none)
92 KB (internal RAM: 60 KB, expanded internal RAM: 32 KB)
76 KB (internal RAM: 60 KB, expanded internal RAM: 16 KB)
External bus
interface
Bus type
Multiplexed/separate Multiplexed/separate
Address bus
24 bits 24 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
3 3
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
93*
1
/97*
2
(including one NMI for each) 99*
1
/103*
2
(including one NMI for each)
External
11 (11)*
3
(including one NMI) 11 (11)*
3
(including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
3 ch
16-bit timer/event counter (TMP)
×
9 ch (encoder count function: 2 ch)
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
3 ch
16-bit timer/event counter (TMP)
×
9 ch (encoder count function: 2 ch)
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
UART/CSI
×
1ch, UART/I
2
C
×
2ch, CSI/I
2
C
×
1ch, UART
×
1ch,
UART (FIFO compatible)
×
2ch, CSI
×
3ch, I
2
C
×
1ch
or
UART/CSI
×
1ch, UART/I
2
C
×
1ch, UART/CSI/I
2
C
×
1ch, CSI/I
2
C
×
1ch, UART
×
1ch, UART (with FIFO)
×
2ch, CSI
×
2ch, I
2
C
×
1ch
UART/CSI
×
1 ch, UART/I
2
C
×
2 ch, UART/CSI/I
2
C
×
1 ch, UART/CSI (FIFO compatible)
×
1 ch,
CSI/I
2
C
×
1 ch, UART
×
1 ch, UART (FIFO compatible)
×
2 ch, CSI
×
3 ch, CSI (FIFO compatible)
×
1 ch, I
2
C
×
2 ch
or
UART/CSI
×
1 ch, CSI/I
2
C
×
2 ch, UART
×
5 ch, UART (FIFO compatible)
×
2 ch, CSI
×
3 ch, CSI (FIFO compatible)
×
2 ch, I
2
C
×
4 ch
A/D converter
10 bits
×
16 ch 10 bits
×
16 ch
D/A converter
8 bits
×
2 ch 8 bits
×
2 ch
DMA controller
4 ch 4 ch
Ports I/O
128 156
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
Real-time counter (Watch timer): 1 ch
IEBus controller/CAN controller*
4
: 1 ch
CAN controller: 2 ch*
5
ROM correction: 8 points
Real-time output
LVI/clock monitor/CRC, SSCG
Watch timer: 1 ch
Real-time counter (Watch timer): 1 ch
IEBus controller/CAN controller*
6
: 1 ch
CAN controller: 2 ch*
7
ROM correction: 8 points
Real-time output
LVI/clock monitor/CRC, SSCG
Operating frequency
When using main clock: 48 MHz (max.)
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 48 MHz (max.)
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, D/A converter: 3.0 V to 3.6 V)
2.85 V to 3.6 V (A/D converter, D/A converter: 3.0 V to 3.6 V)
Package
144-pin LQFP (20
×
20 mm) 176-pin LQFP (24
×
24 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. Products with 1 ch CAN only
*2. Products with 2 ch CAN only
*3. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*4. µPD70F3932 *6. µPD70F3481, 3487, 3926
*5. µPD70F3933 *7. µPD70F3482, 3488, 3927
Generic Name
V850ES/SG2-H V850ES/SG2
Part No.
µPD703282HY µPD703283HY µPD70F3283HY µPD703280Y µPD703281Y µPD70F3281Y µPD703282Y µPD703283Y µPD70F3283Y
CPU name
V850ES V850ES
CPU performance (Dhrystone)
66 MIPS (@ 32 MHz) 43 MIPS (@ 20 MHz)
Internal ROM
512 KB (mask) 640 KB (mask) 640 KB (ash) 256 KB (mask) 384 KB (mask) 384 KB (ash) 512 KB (mask) 640 KB (mask)
640 KB (ash)
Internal RAM
40 KB 48 KB 24 KB 32 KB 40 KB 48 KB
External bus
interface
Bus type
Multiplexed/separate Multiplexed/separate
Address bus
22 bits 22 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
- -
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
51 (including one NMI) 52 (including one NMI)
External
9 (9)* (including one NMI) 9 (9)* (including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
A/D converter
10 bits
×
12 ch 10 bits
×
12 ch
D/A converter
8 bits
×
2 ch 8 bits
×
2 ch
DMA controller
4 ch 4 ch
Ports I/O
84 84
Input
- -
Debug control unit
-
Provided (RUN/break)
-
Provided (RUN/break)
-
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
CAN controller: 1 ch
ROM correction: 4 points
Real-time output
Clock monitor/CRC
Watch timer: 1 ch
CAN controller: 1 ch
ROM correction: 4 points
Real-time output
LVI/clock monitor/CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
Power supply voltage
3.0 V to 3.6 V 2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm) 100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/SJ2-H V850ES/SJ2
Part No.
On-chip
CAN
1 ch
µPD703285HY µPD703286HY
µPD70F3286HY
µPD703284Y µPD70F3284Y µPD703285Y µPD703286Y µPD70F3286Y
2 ch
µPD703287HY µPD703288HY
µPD70F3288HY
− − µPD703287Y µPD703288Y µPD70F3288Y
CPU name V850ES V850ES
CPU performance (Dhrystone) 66 MIPS (@ 32 MHz) 43 MIPS (@ 20 MHz)
Internal ROM 512 KB (mask) 640 KB (mask) 640 KB (ash) 384 KB (mask) 384 KB (ash) 512 KB (mask) 640 KB (mask) 640 KB (ash)
Internal RAM 40 KB 48 KB 32 KB 40 KB 48 KB
External bus
interface
Bus type Multiplexed/separate Multiplexed/separate
Address bus 24 bits 24 bits
Data bus 8/16 bits 8/16 bits
Chip select signal
4 4
Memory controller SRAM, etc. SRAM, etc.
Interrupt sources Internal 64*
1
/68*
2
(including one NMI for each) 65*
1
/69*
2
(including one NMI for each)
External 10 (10)*
3
(including one NMI) 10 (10)*
3
(including one NMI)
Timer/counter 16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
9 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
9 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer 1 ch 1 ch
Serial interface CSI
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)
×
1 ch
CSI
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)
×
1 ch
A/D converter 10 bits
×
16 ch 10 bits
×
16 ch
D/A converter 8 bits
×
2 ch 8 bits
×
2 ch
DMA controller 4 ch 4 ch
Ports I/O 128 128
Input
- -
Debug control unit
-
Provided (RUN/break)
-
Provided (RUN/break)
-
Provided (RUN/break)
Other peripheral functions Watch timer: 1 ch
CAN controller: 1 ch*
4
CAN controller: 2 ch*
5
ROM correction: 4 points
Real-time output
Clock monitor/CRC
Watch timer: 1 ch
CAN controller: 1 ch*
6
CAN controller: 2 ch*
7
ROM correction: 4 points
Real-time output
LVI/clock monitor/CRC
Operating frequency When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
Power supply voltage 3.0 V to 3.6 V 2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V)
Package 144-pin LQFP (20
×
20 mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. Products with 1 ch CAN only
*2. Products with 2 ch CAN only
*3. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*4. µPD703285HY/3286HY/F3286HY only *6. µPD703284Y/F3284Y/3285Y/3286Y/F3286Y only
*5. µPD703287HY/3288HY/F3288HY only *7. µPD703287Y/3288Y/F3288Y only
Generic Name
V850ES/SG1
Part No.
µPD703253Y
CPU name
V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz)
Internal ROM
128 KB (mask)
Internal RAM
8 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
-
Memory controller
SRAM, etc.
Interrupt sources Internal
43 (including one NMI)
External
9 (9)* (including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
Watchdog timer
1 ch
Serial interface
CSI
×
2 ch
CSI/I
2
C
×
1 ch
UART
×
2 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
12 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
84
Input
-
Debug control unit
-
Other peripheral functions
Watch timer: 1 ch, CAN controller: 1 ch
ROM correction: 4 points, clock monitor
Operating frequency
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
Power supply voltage
2.85 V to 3.6 V
(A/D converter: 3.0 V to 3.6 V) (@ 20 MHz)
Package
100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
78 79
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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