Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 27
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3 V Operation 3 V Operation
Generic Name
V850ES/JE3-L V850ES/JF3-L
Part No.
µPD70F3805 µPD70F3806 µPD70F3807 µPD70F3808 µPD70F3840 µPD70F3735 µPD70F3736
CPU name
V850ES V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz) 43 MIPS (@ 20 MHz)
Internal ROM
16 KB (ash) 32 KB (ash) 64 KB (ash) 128 KB (ash) 256 KB (ash) 128 KB (ash) 256 KB (ash)
Internal RAM
8 KB 16 KB 8 KB 16 KB
External bus
interface
Bus type
-
Multiplexed
Address bus
-
18 bits
Data bus
-
8/16 bits
Chip select signal
- -
Memory controller
-
SRAM, etc.
Interrupt sources Internal
49 (Including one NMI) 40 (including one NMI)
External
9 (9)* (Including one NMI) 9 (9)* (including one NMI)
Timer/counter
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
1 ch
A/D converter
10 bits
×
10 ch 10 bits
×
8 ch
D/A converter
8 bits
×
1 ch 8 bits
×
1 ch
DMA controller
4 ch 4 ch
Ports I/O
50 66
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch, real-time output, LVI/clock monitor, CRC Watch timer: 1 ch, real-time output, LVI/clock monitor, CRC
Operating frequency
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.2 V to 3.6 V (A/D converter: 2.7 V to 3.6 V) 2.2 V to 3.6 V (A/D converter: 2.7 V to 3.6 V)
Package
64-pin LQFP (10
×
10 mm), 64-pin FBGA (5
×
5 mm) 80-pin LQFP (12
×
12 mm), 80-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JG3-L
Part No.
µPD70F3737 µPD70F3738 µPD70F3792 µPD70F3793 µPD70F3794 µPD70F3795 µPD70F3796 µPD70F3841 µPD70F3842 µPD70F3843 µPD70F3844
CPU name
V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz)
Internal ROM
128 KB (ash) 256 KB (ash) 384 KB (ash) 512 KB (ash) 256 KB (ash) 384 KB (ash) 512 KB (ash) 768 KB (ash) 1 MB (ash) 768 KB (ash) 1 MB (ash)
Internal RAM
8 KB 16 KB 32 KB 40 KB 80 KB*
1
External bus
interface
Bus type
Multiplexed/separate
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
-
Memory controller
SRAM, etc
-
Interrupt sources Internal
48 (Including one NMI) 55 (Including one NMI)
External
9 (9)*
2
(Including one NMI)
Timer/counter
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
CSI
×
3 ch
UART (LIN compatible)
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
A/D converter
10 bits
×
12 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
84 83 80 83 80
Input
-
Debug control unit
Provided (RUN/break)
USB controller
-
USB function (full-speed)
×
1 ch
-
USB function (full-speed)
×
1 ch
Other peripheral functions
Watch timer: 1 ch, real-time output,
LVI/clock monitor, CRC
Real-time counter (RTC), watch timer: 1 ch, real-time output,
LVI/clock monitor, CRC
Operating frequency
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.2 V to 3.6 V
(A/D converter: 2.7 V to 3.6 V)
2.0 V to 3.6 V
(A/D converter: 2.7 V to 3.6 V)
2.0 V to 3.6 V
(A/D converter: 2.7 V to 3.6 V,
USB controller: 3.0 V to 3.6 V)
2.0 V to 3.6 V
(A/D converter: 2.7 V to 3.6 V)
2.0 V to 3.6 V
(A/D converter: 2.7 V to 3.6 V,
USB controller: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm)
100-pin LQFP (14
×
20 mm)
121-pin FBGA (8
×
8 mm)
100-pin LQFP (14
×
14 mm)
121-pin FBGA (8
×
8 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. 24 bytes is expanded internal RAM.
*2. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JG3 V850ES/JJ3
Part No.
µPD70F3739 µPD70F3740 µPD70F3741 µPD70F3742 µPD70F3743 µPD70F3744 µPD70F3745 µPD70F3746
CPU name
V850ES V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz) 69 MIPS (@ 32 MHz)
Internal ROM
384 KB (ash) 512 KB (ash) 768 KB (ash) 1024 KB (ash) 384 KB (ash) 512 KB (ash) 768 KB (ash)
1024 KB (ash)
Internal RAM
32 KB 40 KB 60 KB 60 KB 32 KB 40 KB 60 KB
External bus
interface
Bus type
Multiplexed/separate Multiplexed/separate
Address bus
22 bits 24 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
-
4
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
48 (including one NMI) 61 (including one NMI)
External
9 (9)* (including one NMI) 10 (10)* (including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
9 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
CSI
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)
×
1 ch
A/D converter
10 bits
×
12 ch 10 bits
×
16 ch
D/A converter
8 bits
×
2 ch 8 bits
×
2 ch
DMA controller
4 ch 4 ch
Ports I/O
84 128
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch, real-time output, LVI/clock monitor, CRC, RAM retention ag Watch timer: 1 ch, real-time output, LVI/clock monitor, CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/ST2
Part No.
µPD703220
CPU name
V850ES
CPU performance (Dhrystone)
-
Internal ROM
ROMless
Internal RAM
48 KB
External bus
interface
Bus type
Separate (multiplexed selectable only for CS1)
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
4
Memory controller
SRAM, etc.
Interrupt sources Internal
28 (including one NMI)
External
9 (including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
Watchdog timer
1 ch
Serial interface
CSI
×
1 ch
CSI/UART
×
1 ch
UART
×
1 ch
A/D converter
10 bits
×
8 ch
D/A converter
8 bits
×
2 ch
DMA controller
-
Ports I/O
57
Input
8
Debug control unit
-
Other peripheral functions
Real-time output
Operating frequency
20 to 34 MHz
Power supply voltage
3.0 V to 3.6 V
Package
120-pin TQFP (14
×
14 mm)
144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
Low-End Lineup (8/10)Low-End Lineup (7/10)
52 53
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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