Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 37
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Noté. / 5. Basé sur avis des utilisateurs
ASSP Lineup (Dashboard Control, Body Control) (10/10)
Generic Name
V850E/IA1
Part No.
µPD703116 µPD70F3116
CPU name
V850E1
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz)
Internal ROM
256 KB (mask) 256 KB (ash)
Internal RAM
10 KB
External bus
interface
Bus type
Multiplexed
Address bus
24 bits
Data bus
8/16 bits
Chip select signal
8
Memory controller
SRAM, etc.
Interrupt sources Internal
45
External
20 (14)* (including one NMI)
Timer/counter
16-bit 3-phase inverter control PWM timer
×
2 ch
16-bit encoder counter/timer
×
2 ch
16-bit timer/counter
×
2 ch
16-bit timer/event counter
×
1 ch
16-bit interval timer
×
1 ch
Watchdog timer
-
Serial interface
CSI
×
2 ch
UART
×
3 ch
A/D converter
10 bits
×
8 ch, 2 units
D/A converter
-
DMA controller
4 ch
Ports I/O
75
Input
8
Debug control unit
-
Other peripheral functions
CAN controller
×
1 ch
Operating frequency
4 to 50 MHz
Power supply voltage
3.0 V to 3.6 V (internal)
4.5 V to 5.5 V (external)
Package
144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C (110
°
C version also available)
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
ASSP Lineup (CAN) (1/7)
Generic Name
V850E2/MN4 (Under development)
Part No.
µPD70F3512 µPD70F3514 µPD70F3515
CPU name
V850E2M V850E2M
×
2
CPU performance (Dhrystone)
512 MIPS (@ 200 MHz)
Internal ROM
1 MB (ash) 2 MB (ash)
Internal RAM
64 KB 64 KB
×
2
External bus
interface
Bus type
Separate (2 channels)
Address bus
26 bits, 26 bits
Data bus
8/16/32 bits, 16/32 bits
Chip select signal
4, 5
Memory controller
SDRAM, SRAM, etc.
Interrupt sources Internal
190 196
External
29 (including one NMI)
Timer/counter
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
4 units
16-bit encoder timer: 2 ch
Watchdog timer
1 ch 2 ch
Serial interface
UART/CSI
×
4 ch
UART/CSI/I
2
C
×
4 ch*
1
UART/CSI/I
2
C/CAN
×
2 ch*
2
A/D converter
12 bits
×
12 ch (5 V analog), 10 bits
×
12 ch (3.3 V analog)
D/A converter
-
DMA controller
16 ch
Ports I/O
181
Input
7
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
USB 2.0 host (full-speed)
×
1 ch
Ethernet controller
1 ch
Other peripheral functions
Hardware bus common memory: 64 KB, hardware bus side cache: 16 KB, dedicated DMA for secondary memory controller, inverter timer support, boundary scan
Operating frequency
144 to 200 MHz
Power supply voltage
1.1 V to 1.3 V (internal)/3.0 V to 3.6 V (external)/analog: 3.0 V to 3.6 V or 4.5 V to 5.5 V*
3
Package
304-pin FBGA (19
×
19 mm)
Operating ambient temperature
-
40
°
C to
+
100
°
C*
4
*1. Of which, 3 UART/SCII channels have FIFO function.
*2. Of which, 1 UART/SCII channel have FIFO function.
*3. 10-bit precision when using 3.3 V analog power supply, 12-bit precision when using 5 V analog power supply
*4. Package surface temperature
Generic Name
V850E2/ML4 (Under development)
Part No.
µPD70F3510 µPD70F3514
CPU name
V850E2M
CPU performance (Dhrystone)
512 MIPS (@ 200 MHz)
Internal ROM
768 KB (ash) 1 MB (ash)
Internal RAM
64 KB
+
expanded RAM: 64 KB
External bus
interface
Bus type
Separate
Address bus
26 bits
Data bus
8/16/32 bits
Chip select signal
4
Memory controller
SDRAM, SRAM, etc.
Interrupt sources Internal
150
External
29 (including one NMI)
Timer/counter
16-bit timer array: 16 ch
×
2 unit
32-bit timer array: 4 ch
×
1 units
16-bit encoder timer: 2 ch
Watchdog timer
1 ch
Serial interface
UART
×
4 ch (of which, 2 have FIFO function)
CSI
×
4 ch (of which, 2 have FIFO function)
I
2
C
×
2 ch
A/D converter
10 bits or 12 bits
×
12 ch (5 V input for 12-bit)
D/A converter
-
DMA controller
8 ch (4 ch for internal transfers only)
Ports I/O
119
Input
1
Debug control unit
Provided (RUN/break/trace)
USB controller
USB 2.0 function (full-speed)
×
1 ch
USB 2.0 host (full-speed)
×
1 ch
Ethernet controller
1 ch
Other peripheral functions
CAN, FPU
Operating frequency
200 MHz
Power supply voltage
1.2 V and 3.3 V (
+
5 V (12-bits A/D)
Package
216-pin QFP (24
×
24 mm)
Operating ambient temperature
-
40
°
C to
+
100
°
C*
* Package surface temperature
72 73
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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