Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 23
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Features
Rewrite Modes
Handshake-compatible CSI communication method
CSI communication method UART communication method
Dedicated ash
memory programmer
(PG-FP5, etc.)
Example: V850ES/JG3
VDD
VSS
RESET
SIB0, SIB3
SOB0, SOB3
SCKB0, SCKB3
V
DD
GND
RESET
SO
SI
SCK
FLMD1FLMD1
FLMD0FLMD0
Dedicated ash
memory programmer
(PG-FP5, etc.)
Example: V850ES/JG3
V
DD
V
SS
RESET
SIB0, SIB3
SOB0, SOB3
SCKB0, SCKB3
PCM0
V
DD
GND
RESET
SO
SI
SCK
HS
FLMD1FLMD1
FLMD0FLMD0
Dedicated ash
memory programmer
(PG-FP5, etc.)
Example: V850ES/JG3
FLMD1
V
DD
VSS
RESET
RXDA0
TXDA0
FLMD1
FLMD0FLMD0
V
DD
GND
RESET
TxD
RxD
Programming using programmer (on-board/off-board)
The ash memory can be erased and rewritten using a self-
programming library in a program placed in an area outside
the ash memory.
Self-programming mode (single-power-supply method)
Self-programming flow
All blocks completed?
YES
NO
Erase processing
Flash environment initialization processing
Write processing
Internal verify processing
Flash environment end processing
Processing end
Flash information setting processing
Boot area replacement processing
Flash memory operation
• Access to ash area prohibited
• STOP instruction execution
prohibited
• Clock stop prohibited
256 KB
Flash memory
Library initialization
processing
Library end
processing
00000H
3FFFFH
Block
7 (60 KB)
Block
6 (60 KB)
Block
5 (60 KB)
Block
4 (60 KB)
Block
3 (4 KB)
Block
2 (4 KB)
Block
1 (4 KB)
Block
0 (4 KB)
Flash memory
Normal operation mode Self-programming mode
00000H
3FFFFH
Self-programming
library
(erase/write
routine execution)
Caution The number of blocks and block capacity differ depending on the product.
(Example: V850ES/SA2)
To reduce your development time and improve maintenance after shipping, Renesas Electronics offers V850 microcontrollers with
on-chip ash memory from 16 KB to 2048 KB. Our ash memory microcontrollers offer the following features:
Flash capacity
16 to 2048 KB
Overwrite unit
Entire memory at one time, or block units
Rewrite method
Serial communication using dedicated ash memory
programmer (on-board, off-board)
Self-ash programming
Rewrite voltage
Single-power-supply ash: Operating voltage
Dual-power-supply ash: Operating voltage 7.8 V
Rewrite count: 100/1,000/20,000 times
So that you can use the same microcontroller from development to mass production and maintenance, our V850 microcontrollers
provide a programmer rewrite mode that uses serial communication to enable on-board programming, as well as a self-programming
mode that enables the ash memory to be rewritten by using a user-created program:
On-board programming mode
This programming mode is used to rewrite the ash memory mounted on the target system using a dedicated ash memory programmer.
Off-board programming mode
This programming mode is used to rewrite the ash memory using a dedicated ash memory programmer and dedicated program adapter
(FA Series*
1
).
Self-programming mode
This programming mode is used to rewrite the ash memory by executing a user-created program written beforehand to the ash memory
by using on-board/off-board programming*
2
.
* 1. The FA Series is a product of Naito Densei Machida Mfg. Co., Ltd.
2. Since instruction fetch and data access cannot be performed from the internal ash memory area during self-programming, a program for rewriting the
internal RAM or external memory must be transferred in advance.
Flash Specification List
CPU Product
Max. Operating
Frequency
Rewrite Voltage
Rewrite Mode
Rewrite
Count
(Times)
On-Board/Off-Board
Programming
Self-
Programming
VDD VPP CSI UART CSI+HS
V850E
V850E/MA3 80 MHz
2.3 V to 2.7 V (internal),
3.0 V to 3.6 V (external)
–
√ √ √ √
100
V850E/IG4, IH4 100 MHz
1.35 V to 1.65 V (internal),
4.0 V to 5.5 V (external)
–
√ √ √ √
100
V850E/IG4-H, IH4-H 100 MHz
1.35 V to 1.65 V (internal),
4.0 V to 5.5 V (external)
–
√ √ √ √
100
V850E/IF3, IG3 64 MHz 3.5 V to 5.5 V –
√ √ √ √
100
V850E/IA3, IA4 64 MHz
2.3 V to 2.7 V (internal),
4.5 V to 5.5 V (external)
–
√ √ √ √
100
V850E/IA2 40 MHz
4.5 V to 5.5 V
(using regulator)
7.8 V
√ √ √
– 100
V850E/IA1 50 MHz
3.0 V to 3.6 V (internal),
4.5 V to 5.5 V (external)
7.8 V
√ √ √
– 100
V850E/DG3 16 MHz 4.0 V to 5.5 V –
√ √ √ √
100
V850E/DJ3 64 MHz/32 MHz 4.0 V to 5.5 V –
√ √ √ √
100
V850E/DL3 64 MHz 4.0 V to 5.5 V –
√ √ √ √
100
V850E/SJ3-H, SK3-H 48 MHz 2.85 V to 3.6 V –
√ √ √ √
1000
V850ES
V850ES/HE3, HF3, HG3, HJ3 32 MHz 3.8 V to 5.5 V –
√ √ √ √
1000
V850ES/IE2 20 MHz 3.5 V to 5.5 V –
√ √ √ √
100
V850E/JE3-E, JF3-E, JG3-E, JH3-E, JJ3-E 50 MHz 2.85 V to 3.6 V –
√ √ √ √
1000
V850ES/JC3-H, JE3-H, JG3-H, JH3-H, JG3-U, JH3-U
48 MHz 2.85 V to 3.6 V –
√ √ √ √
1000
V850ES/JG3, JJ3 32 MHz 2.85 V to 3.6 V –
√ √ √ √
1000
V850ES/JC3-L, JE3-L, JF3-L, JG3-L 20 MHz 2.7 V to 3.6 V –
√ √ √ √
1000
V850ES/IK1 32 MHz 3.5 V to 5.5 V –
√ √ √ √
100
V850ES/FE3, FF3, FG3, FJ3, FK3 48 MHz/32 MHz 3.3 V to 5.5 V –
√ √ √ √
1000
V850ES/FE3-L, FF3-L, FG3-L 20 MHz 3.3 V to 5.5 V –
√ √ √ √
1000
V850ES/FE2, FF2, FG2, FJ2 20 MHz 3.5 V to 5.5 V –
√ √ √ √
100
V850ES/SG3, SJ3 32 MHz 3.0 V to 3.6 V –
√ √ √ √
1000
V850ES/SG2-H, SJ2-H 32 MHz 3.0 V to 3.6 V –
√ √ √ √
100
V850ES/SG2, SJ2 20 MHz 3.0 V to 3.6 V –
√ √ √ √
100
V850E2
V850E2/MN4 200 MHz
1.1 V to 1.3 V (internal),
3.0 V to 3.6 V (external)
3.0 V to 3.6 V or
4.5 V to 5.5 V (analog)
–
√ √ √ √
100
V850E2/ML4 200 MHz
1.1 V to 1.3 V (internal),
3.0 V to 3.6 V (external)
–
√ √ √ √
100
V850E2/SG4-H, SJ4-H, SK4-H 160 MHz
1.1 V to 1.3 V (internal),
3.0 V to 3.6 V (external)
–
√ √ √ √
20000
V850E2/FG4, FJ4, FK4, FL4 80 MHz 3.0 V to 5.5 V –
√ √ √ √
100
V850E2/FE4-L, FF4-L, FG4-L, FJ4-L, FK4-L 64 MHz/32 MHz 3.0 V to 5.5 V –
√ √ √ √
1000
V850E2/FL4-H 160 MHz 3.0 V to 5.5 V –
√ √ √ √
100
V850E2/FK4-G 80 MHz 3.0 V to 5.5 V –
√ √ √ √
100
V850E2/FE4-M, FF4-M 80 MHz 3.0 V to 5.5 V –
√ √ √ √
100
44 45
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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