Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 41
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Noté. / 5. Basé sur avis des utilisateurs
Generic Name
V850E2/SG4-H (Under planning) V850E2/SJ4-H (Under planning) V850E2/SK4-H (Under development)
Part No.
µPD70F4013 µPD70F4014 µPD70F4015 µPD70F4016 µPD70F4017 µPD70F4018
CPU name
V850E2M V850E2M V850E2M
CPU performance (Dhrystone)
400 MIPS (@ 160 MHz) 400 MIPS (@ 160 MHz) 400 MIPS (@ 160 MHz)
Internal ROM
1 MB (ash) 1.5 MB (ash) 1 MB (ash) 1.5 MB (ash) 1.5 MB (ash) 2 MB (ash)
Internal RAM
96 KB 128 KB 96 KB 128 KB 128 KB 192 KB
Data ash
32 KB 32 KB 32 KB
External bus
interface
Bus type
Multiplexed SRAM I/F SDRAM I/F, multiplexed/separate SRAM I/F SDRAM I/F, multiplexed/separate SRAM I/F
Address bus
20 bits 24 bits 24 bits
Data bus
8/16 bits 8/16 bits 8/16/32 bits
Chip select signal
-
3 4
Memory controller
SRAM, etc. SDRAM, SRAM, etc. SDRAM, SRAM, etc.
Interrupt sources Internal
10 16 16
External
144 161 208
Timer/counter
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
1 unit
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
1 unit
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
2 units
Watchdog timer
2 ch 2 ch 2 ch
Serial interface
UART/CSI
×
4 ch
CSI
×
2 ch
CSI (With FIFO)
×
2 ch
I
2
C
×
4 ch
MediaLB
×
1 ch
UART/CSI
×
5 ch
CSI
×
2 ch
CSI (With FIFO)
×
3 ch
I
2
C
×
4 ch
MediaLB
×
1 ch
UART/CSI
×
5 ch
CSI
×
2 ch
CSI (With FIFO)
×
3 ch
I
2
C
×
4 ch
MediaLB
×
1 ch
A/D converter
10 bits
×
8 ch
×
1 unit 10 bits
×
16 ch
×
1 unit 10 bits
×
16 ch
×
1 unit
D/A converter
- - -
DMA controller
16 ch 16 ch 16 ch
Ports I/O
58 100 127
Input
- - -
Debug control unit
Provided (RUN/break) Provided (RUN/break) Provided (RUN/break)
Ethernet controller
- -
1 ch
Other peripheral functions
IEBus controller/CAN controller: 1 ch
Power-on clear (option), LVI, clock monitor, data CRC,
Hardware bus common memory: 32 KB, SSCG
IEBus controller: 1 ch
CAN controller: 2 ch
Power-on clear (option), LVI, clock monitor, data CRC,
Hardware bus common memory: 32 KB, SSCG
IEBus controller: 1 ch
CAN controller: 2 ch
Power-on clear (option), LVI, clock monitor, data CRC,
Hardware bus common memory: 32 KB, SSCG
Operating frequency
When using main clock: 160 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 160 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 160 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
1.1 V to 1.3 V (internal)/3.0 V to 3.6 V (external) 1.1 V to 1.3 V (internal)/3.0 V to 3.6 V (external) 1.1 V to 1.3 V (internal)/3.0 V to 3.6 V (external)
Package
100-pin LQFP (14
×
14 mm) 144-pin LQFP (20
×
20 mm) 176-pin LQFP (24
×
24 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
105
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
105
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
105
°
C
Numbers of channels indicate the total number implemented on the product. The actual number of usable channels differs depending on multi-use pin settings.
ASSP Lineup (Car Audio/Vehicle Navigation Control) (1/4) ASSP Lineup (Car Audio/Vehicle Navigation Control) (2/4)
Generic Name
V850ES/SG1
Part No.
µPD703252Y
CPU name
V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz)
Internal ROM
256 KB (mask)
Internal RAM
12 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
-
Memory controller
SRAM, etc.
Interrupt sources Internal
36 (including one NMI)
External
9 (9)* (including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
5 ch
Watchdog timer
1 ch
Serial interface
CSI
×
2 ch
CSI/I
2
C
×
1 ch
UART
×
2 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
12 ch
D/A converter
-
DMA controller
-
Ports I/O
84
Input
-
Debug control unit
-
Other peripheral functions
Watch timer: 1 ch, IEBus controller: 1 ch
ROM correction: 4 points, clock monitor
Operating frequency
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 200 kHz
Power supply voltage
2.85 V to 3.6 V
(A/D converter: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm)
100-pin QFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/SG3
Part No. On-chip IEBus
µPD70F3333 µPD70F3334 µPD70F3340 µPD70F3341 µPD70F3342 µPD70F3343
On-chip IEBus/CAN
µPD70F3335 µPD70F3336 µPD70F3350 µPD70F3351 µPD70F3352 µPD70F3353
CPU name
V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 512 KB (ash) 640 KB (ash) 768 KB (ash) 1024 KB (ash)
Internal RAM
24 KB 32 KB 40 KB 48 KB 60 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
-
Memory controller
SRAM, etc.
Interrupt
sources
Internal
52 (including one NMI)
External
9 (9)*
1
(including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
6 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
A/D converter
10 bits
×
12 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
84
Input
-
Debug control unit
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
IEBus controller/CAN controller*
2
: 1 ch
ROM correction: 4 points
Real-time output
LVI/clock monitor/CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V)
Package
100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*2. µPD70F3335/F3336/F3350/F3351/F3352/F3353 only
*1. Products without CAN, product with 1 ch CAN only
*2. Products with 2 ch CAN only
*3. The gures in parentheses indicate the number of external interrupts that can be used to release STOP mode.
*4. µPD70F3354/F3355/F3356/F3357/F3358 only
*5. µPD70F3364/F3365/F3366/F3367/F3368 only
Generic Name
V850ES/SJ3
Part No. On-chip IEBus
µPD70F3344 µPD70F3345 µPD70F3346 µPD70F3347 µPD70F3348
On-chip IEBus/CAN (1 ch)
µPD70F3354 µPD70F3355 µPD70F3356 µPD70F3357 µPD70F3358
On-chip IEBus/CAN (1 ch), CAN (1 ch)
µPD70F3364 µPD70F3365 µPD70F3366 µPD70F3367 µPD70F3368
CPU name
V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz)
Internal ROM
384 KB (ash) 512 KB (ash) 640 KB (ash) 768 KB (ash) 1024 KB (ash)
Internal RAM
32 KB 40 KB 48 KB 60 KB
External bus
interface
Bus type
Multiplexed/separate
Address bus
24 bits
Data bus
8/16 bits
Chip select signal
4
Memory controller
SRAM, etc.
I n t e r r u p t
sources
Internal
65*
1
/69*
2
(including one NMI for each)
External
10 (10)*
3
(including one NMI)
Timer/counter
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
9 ch
16-bit timer/event counter (TMQ)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI
×
4 ch
UART (LIN compatible)/CSI
×
1 ch
CSI/I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
2 ch
UART (LIN compatible)
×
1 ch
A/D converter
10 bits
×
16 ch
D/A converter
8 bits
×
2 ch
DMA controller
4 ch
Ports I/O
128
Input
-
Debug control unit
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
IEBus controller/CAN controller*
4
: 1 ch
CAN controller: 2 ch*
5
ROM correction: 4 points
Real-time output
LVI/clock monitor/CRC
Operating frequency
When using main clock: 2.5 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter: 3.0 V to 3.6 V)
Package
144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
80 81
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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