Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 36
- Page / 51
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
ASSP Lineup (Dashboard Control, Body Control) (9/10)ASSP Lineup (Dashboard Control, Body Control) (8/10)
Generic Name
V850ES/FE3-L
Part No.
µPD70F3610 µPD70F3611 µPD70F3612 µPD70F3613 µPD70F3614
CPU name
V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz)
Internal ROM
64 KB (ash) 96 KB (ash) 128 KB (ash) 192 KB (ash) 256 KB (ash)
Internal RAM
6 KB 6 KB 8 KB 12 KB 16 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
39 (including one NMI)
External
9 (9)*
1
(including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
5 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
10 ch
D/A converter
-
DMA controller
-
Ports I/O
51
Input
-
Debug control unit
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
CAN controller: 1 ch
Key input interrupt: 8 ch
Clock monitor/POC/LVI/PCL output
Operating frequency
When using main clock: 4 to 20 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
64-pin LQFP (10
×
10 mm)
64-pin LQFP (7
×
7 mm)
64-pin LQFP (10
×
10 mm)
64-pin LQFP (7
×
7 mm)*
2
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*2. µPD70F3614 only
Generic Name
V850ES/FF3-L V850ES/FG3-L
Part No.
µPD70F3615 µPD70F3616 µPD70F3617 µPD70F3618 µPD70F3619 µPD70F3620 µPD70F3621 µPD70F3622
CPU name
V850ES V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz) 43 MIPS (@ 20 MHz)
Internal ROM
64 KB (ash) 96 KB (ash) 128 KB (ash) 192 KB (ash) 256 KB (ash) 128 KB (ash) 192 KB (ash) 256 KB (ash)
Internal RAM
6 KB 6 KB 8 KB 12 KB 16 KB 8 KB 12 KB 16 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
39 (including one NMI) 42 (including one NMI)
External
9 (9)* (including one NMI) 12 (12)* (including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
5 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)
×
3 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
12 ch 10 bits
×
16 ch
D/A converter
- -
DMA controller
- -
Ports I/O
67 84
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
CAN controller: 1 ch
Key input interrupt: 8 ch
Clock monitor/POC/LVI/PCL output
Watch timer: 1 ch
CAN controller: 1 ch
Key input interrupt: 8 ch
Clock monitor/POC/LVI/PCL output
Operating frequency
When using main clock: 4 to 20 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 20 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
80-pin LQFP (12
×
12 mm) 100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/FE2 V850ES/FF2
Part No.
µPD703230B µPD703231B µPD70F3231B µPD703232B µPD70F3232B µPD703233B µPD70F3233B
CPU name
V850ES V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz) 43 MIPS (@ 20 MHz)
Internal ROM
64 KB (mask) 128 KB (mask) 128 KB (ash) 128 KB (mask) 128 KB (ash) 256 KB (mask) 256 KB (ash)
Internal RAM
4 KB 6 KB 6 KB 12 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
36 (including one NMI) 36 (including one NMI)
External
9 (9)* (including one NMI) 9 (9)* (including one NMI)
Timer/counter
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
A/D converter
10 bits
×
10 ch 10 bits
×
12 ch
D/A converter
- -
DMA controller
- -
Ports I/O
51 67
Input
- -
Debug control unit
-
Provided (RUN/break)
-
Provided (RUN/break)
-
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch, POC/LVI, RAM retention ag, CAN controller: 1 ch Watch timer: 1 ch, POC/LVI, RAM retention ag, CAN controller: 1 ch
Operating frequency
When using main clock: 4 to 20 MHz When using main clock: 4 to 20 MHz
Power supply voltage
3.5 V to 5.5 V 3.5 V to 5.5 V
Package
64-pin LQFP (10
×
10 mm) 80-pin TQFP (12
×
12 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/FG2 V850ES/FJ2
Part No.
µPD703234B µPD70F3234B µPD703235B µPD70F3235B µPD70F3236B µPD70F3237B µPD70F3238B µPD70F3239B
CPU name
V850ES V850ES
CPU performance (Dhrystone)
43 MIPS (@ 20 MHz) 43 MIPS (@ 20 MHz)
Internal ROM
128 KB (mask) 128 KB (ash) 256 KB (mask) 256 KB (ash) 384 KB (ash) 256 KB (ash) 376 KB (ash) 512 KB (ash)
Internal RAM
6 KB 12 KB 16 KB 12 KB 20 KB
External bus
interface
Bus type
-
Multiplexed
Address bus
-
16 bits
Data bus
-
8/16 bits
Chip select signal
-
4
Memory controller
-
SRAM, etc.
Interrupt sources Internal
51 (including one NMI) 58 (including one NMI) 68 (including one NMI)
External
12 (12)* (including one NMI) 16 (16)* (including one NMI)
Timer/counter
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMQ)
×
2 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMQ)
×
3 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
3 ch
CSI
×
3 ch
UART (LIN compatible)
×
3 ch
CSI
×
3 ch
UART (LIN compatible)
×
4 ch
A/D converter
10 bits
×
16 ch 10 bits
×
24 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
84 128
Input
- -
Debug control unit
-
Provided (RUN/break)
-
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch, POC/LVI, RAM retention ag, CAN controller: 2 ch
Watch timer: 1 ch, POC/LVI, RAM retention ag
CAN controller: 2 ch CAN controller: 4 ch
Operating frequency
When using main clock: 4 to 20 MHz When using main clock: 4 to 20 MHz
Power supply voltage
3.5 V to 5.5 V 3.5 V to 5.5 V
Package
100-pin LQFP (14
×
14 mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
70 71
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
Produits connexes et manuels pour Mise en réseau Renesas Single-Chip Microcomputer M34519T-MCU
(63 pages)
(46 pages)© 2020, manymanuals.fr. Tous droits réservés | 0.041 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels