Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 35
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ASSP Lineup (Dashboard Control, Body Control) (7/10)ASSP Lineup (Dashboard Control, Body Control) (6/10)
Generic Name
V850ES/FE3 V850ES/FF3 V850ES/FG3
Part No.
µPD70F3370A µPD70F3371 µPD70F3372 µPD70F3373 µPD70F3374 µPD70F3375 µPD70F3376A µPD70F3377A
CPU name
V850ES V850ES V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz) 69 MIPS (@ 32 MHz) 69 MIPS (@ 32 MHz) 98 MIPS (@ 48 MHz)
Internal ROM
128 KB (ash) 256 KB (ash) 128 KB (ash) 256 KB (ash) 128 KB (ash) 256 KB (ash) 384 KB (ash) 512 KB (ash)
Internal RAM
8 KB 16 KB 8 KB 16 KB 8 KB 16 KB 24 KB 32 KB
EEPROM emulation
32 KB 32 KB 32 KB
External bus
interface
Bus type
- - -
Address bus
- - -
Data bus
- - -
Chip select signal
- - -
Memory controller
- - -
Interrupt sources Internal
48 (including one NMI) 48 (including one NMI) 60 (including one NMI) 65 (including one NMI)
External
9 (9)* (including one NMI) 9 (9)* (including one NMI) 12 (12)* (including one NMI) 13 (13)* (including one NMI)
Timer/counter
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch 1 ch
Serial interface
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)
×
2 ch
I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)
×
3 ch
I
2
C
×
1 ch
CSI
×
2 ch
UART (LIN compatible)
×
5 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
10 ch 10 bits
×
12 ch 10 bits
×
16 ch
D/A converter
- - -
DMA controller
4 ch 4 ch 4 ch
Ports I/O
51 67 84
Input
- - -
Debug control unit
Provided (RUN/break) Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
CAN controller: 1 ch
Key input interrupt: 8 ch
Clock monitor/POC/LVI/PCL output, SSCG
Watch timer: 1 ch
CAN controller: 1 ch
Key input interrupt: 8 ch
Clock monitor/POC/LVI/PCL output, SSCG
Watch timer: 1 ch
CAN controller: 2 ch
Key input interrupt: 8 ch
Clock monitor/POC/LVI/PCL output, SSCG
Operating frequency
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 48 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
64-pin LQFP (10
×
10 mm) 80-pin LQFP (12
×
12 mm) 100-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/FJ3 V850ES/FK3
Part No.
µPD70F3378 µPD70F3379 µPD70F3380 µPD70F3381 µPD70F3382 µPD70F3383 µPD70F3384 µPD70F3385
CPU name
V850ES V850ES
CPU performance (Dhrystone)
69 MIPS (@ 32 MHz) 98 MIPS (@ 48 MHz) 98 MIPS (@ 48 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 512 KB (ash) 768 KB (ash) 1024 KB (ash) 512 KB (ash) 768 KB (ash) 1024 KB (ash)
Internal RAM
16 KB 24 KB 32 KB 40 KB 48 KB 32 KB 48 KB 60 KB
EEPROM emulation
32 KB 32 KB
External bus
interface
Bus type
Multiplexed Multiplexed
Address bus
16 bits 16 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
4 4
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
71 (including one NMI) 81 (including one NMI) 83 (including one NMI) 101 (including one NMI)
External
16 (16)*
1
(including one NMI) 17 (17)*
1
(including one NMI)
Timer/counter
16-bit timer/event counter (TAB)
×
3 ch
16-bit timer/event counter (TAA)
×
5 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TAB)
×
3 ch
16-bit timer/event counter (TAA)
×
8 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
3 ch
UART (LIN compatible)
×
3 ch
I
2
C
×
1 ch
CSI
×
3 ch
UART (LIN compatible)
×
6 ch
I
2
C
×
1 ch
CSI
×
4 ch
UART (LIN compatible)
×
6 ch
I
2
C
×
1 ch
CSI
×
4 ch
UART (LIN compatible)
×
8 ch
I
2
C
×
1 ch
A/D converter
10 bits
×
24 ch 10 bits
×
24 ch, 10 bits
×
16 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
128 152
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
CAN controller: 3 ch*
2
CAN controller: 4 ch*
3
Key input interrupt: 8 ch, clock monitor/POC/LVI/PCL output, SSCG
Watch timer: 1 ch
CAN controller: 5 ch
Key input interrupt: 8 ch
Clock monitor/POC/LVI/PCL output, SSCG
Operating frequency
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using high-speed internal
oscillation clock: 8 MHz
When using low-speed internal
oscillation clock: 240 kHz
When using main clock: 4 to 48 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 4 to 48 MHz
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V) 3.3 V to 5.5 V (A/D converter: 4.0 V to 5.5 V)
Package
144-pin LQFP (20
×
20 mm) 176-pin LQFP (24
×
24 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*2. µPD70F3378 only
*3. µPD70F3379/F3380/F3381/F3382 only
Generic Name
V850E2/FE4-M (Under development) V850E2/FF4-M (Under development)
Part No.
µPD70F3540 µPD70F3541 µPD70F3542 µPD70F3543 µPD70F3544 µPD70F3545
CPU name
V850E2M V850E2M
CPU performance (Dhrystone)
205 MIPS (@ 80 MHz) 205 MIPS (@ 80 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 512 KB (ash) 256 KB (ash) 384 KB (ash) 512 KB (ash)
Internal RAM
32 KB 40 KB 48 KB 32 KB 40 KB 48 KB
Data ash
32 KB 32 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
84 84
External
11 12
Timer/counter
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
2 units
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
2 units
Watchdog timer
2 ch 2 ch
Serial interface
UART (LIN compatible)
×
3 ch
CSI
×
2 ch
I
2
C
×
1 ch
CAN controller
×
1 ch
UART (LIN compatible)
×
3 ch
CSI
×
2 ch
I
2
C
×
1 ch
CAN controller
×
1 ch
A/D converter
12 bits
×
12 ch 12 bits
×
12 ch
D/A converter
- -
DMA controller
8 ch 8 ch
Ports I/O
33 49
Input
- -
Debug control unit
Provided (RUN/break/trace) Provided (RUN/break/trace)
Other peripheral functions
POC, LVI, clock monitor, comparator
×
1, random number generator, data CRC, key return: 8 ch POC, LVI, clock monitor, comparator
×
1, random number generator, data CRC, key return: 8 ch
Operating frequency
When using main clock: 80 MHz (max.)
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 80 MHz (max.)
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.0 V to 5.5 V 3.0 V to 5.5 V
Package
64-pin LQFP (10
×
10 mm) 80-pin LQFP (12
×
12 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C,
-
40
°
C to
+
125
°
C
Generic Name
V850E2/FK4-G (Under development) V850E2/FL4-H (Under development)
Part No.
µPD70F3592 µPD70F3564
CPU name
V850E2M V850E2M
CPU performance (Dhrystone)
T.B.D. 324 MIPS (@ 160 MHz)
Internal ROM
1 MB (ash) 2 MB (ash)
Internal RAM
128 KB 144 KB
Data ash
32 KB 64 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
T.B.D. 239
External
17 17
Timer/counter
32-bit timer: 4 ch
×
2 units
16-bit timer: 16 ch
×
2 units
32-bit timer: 4 ch
×
2 units
16-bit timer: 16 ch
×
9 units
Watchdog timer
2 ch 2 ch
Serial interface
UART (LIN compatible)
×
5 ch
CSI
×
2 ch
I
2
C
×
1 ch
CAN controller
×
6 ch
FlexRay controller
×
2 ch
×
1 unit
UART (LIN compatible)
×
12 ch
CSI
×
3 ch
CSI (With FIFO)
×
3 ch
I
2
C
×
1 ch
Ethernet controller
×
1 ch
CAN controller
×
6 ch
FlexRay controller
×
2 ch
×
1 unit
A/D converter
12 bits
×
24 ch
+
12 ch 12 bits
×
24 ch
×
2 units
D/A converter
- -
DMA controller
8 ch 16 ch
Ports I/O
136 161
Input
- -
Debug control unit
Provided (RUN/break/trace) Provided (RUN/break/trace)
Other peripheral functions
POC, LVI, clock monitor, comparator
×
2,
random number generator, data CRC
POC, LVI, clock monitor, comparator
×
2,
random number generator, data CRC, key return: 8 ch
Operating frequency
When using main clock: 80 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 160 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
3.0 V to 5.5 V 3.0 V to 5.5 V
Package
176-pin HLQFP (24
×
24 mm) 208-pin QFP (28
×
28 mm), 256-pin BGA (21
×
21 mm)
Operating ambient temperature
-
40
°
C to
+
110
° -
40
°
C to
+
85
°
C,
-
40
°
C to
+
110
°
C
68 69
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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