Renesas Single-Chip Microcomputer M34519T-MCU Spécifications Page 32
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Noté. / 5. Basé sur avis des utilisateurs
ASSP Lineup (Inverter Control, etc.) (5/5)
Generic Name
V850ES/IK1 V850ES/IE2
Part No.
µPD703327 µPD703329 µPD70F3713 µPD70F3714
µPD70F3329
CPU name
V850ES V850ES
CPU performance (Dhrystone)
63 MIPS (@ 32 MHz) 39 MIPS (@ 20 MHz)
Internal ROM
64 KB (mask)
128 KB (mask)
64 KB (ash) 128 KB (ash)
128 KB (ash)
Internal RAM
4 KB 6 KB 6 KB 6 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
36 (including one NMI) 36 (including one NMI)
External
7 (6)* 7 (6)*
Timer/counter
16-bit timer/event counter (TMQ)
×
1 ch (3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TMP)
×
2 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit timer/counter (TMP)
×
2 ch
16-bit interval timer (TMM)
×
1 ch
16-bit timer/event counter (TMQ)
×
1 ch (3-phase inverter control PWM timer compatible)
16-bit timer/event counter (TMP)
×
2 ch
16-bit timer/event counter (TMQ)
×
1 ch
16-bit timer/counter (TMP)
×
2 ch
16-bit interval timer (TMM)
×
1 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
1 ch
UART
×
2 ch
CSI
×
1 ch
UART
×
2 ch
A/D converter
10 bits
×
4 ch, 2 units (conversion time: 2 µs) 10 bits
×
4 ch, 2 units (conversion time: 3.1 µs)
D/A converter
- -
DMA controller
- -
Ports I/O
39 39
Input
- -
Debug control unit
- -
Other peripheral functions
3-phase inverter control, ROM correction: 4 points, software pull-up, POC/LVI/clock monitor 3-phase inverter control, software pull-up, POC/LVI/clock monitor
Operating frequency
2.5 to 32 MHz 2.5 to 20 MHz
Power supply voltage
3.5 V to 5.5 V (A/D converter: 4.5 V to 5.5 V) 3.5 V to 5.5 V (A/D converter: 4.5 V to 5.5 V)
Package
64-pin LQFP (14
×
14 mm) 64-pin LQFP (14
×
14 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
ASSP Lineup (Dashboard Control, Body Control) (1/10)
Generic Name
V850E/DJ3 V850E/DL3
Part No.
µPD70F3424 µPD70F3425 µPD70F3426 µPD70F3427
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
126 MIPS (@ 64 MHz) 126 MIPS (@ 64 MHz)
Internal ROM
512 KB (ash) 1024 KB (ash) 2048 KB (ash) 1024 KB (ash)
Internal RAM
24 KB 32 KB 84 KB 60 KB
External bus
interface
Bus type
-
Separate
Address bus
-
24 bits
Data bus
-
8/16/32 bits
Chip select signal
-
4
Memory controller
-
SRAM, etc.
Interrupt sources Internal
82 (including one NMI) 82 (including one NMI)
External
9 (9)* (including one NMI) 9 (9)* (including one NMI)
Timer/counter
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMG)
×
3 ch
16-bit interval timer (TMZ)
×
10 ch
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMG)
×
3 ch
16-bit interval timer (TMZ)
×
10 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
3 ch
I
2
C
×
2 ch
UART (LIN compatible)
×
2 ch
CSI
×
3 ch
I
2
C
×
2 ch
UART (LIN compatible)
×
2 ch
A/D converter
10 bits
×
16 ch 10 bits
×
16 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
98 101
Input
16 16
Debug control unit
Provided (RUN/break) Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
Meter driver: 6 ch
ROM correction: 8 points, POC/clock monitor, SSCG
Voltage comparator
Sound generator
LCD bus interface
CAN controller: 2 ch
Watch timer: 1 ch
Meter driver: 6 ch
ROM correction: 8 points, POC/clock monitor
SSCG, Voltage comparator
Sound generator
LCD bus interface
CAN controller: 2 ch
Operating frequency
When using main clock: 4 to 64 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 240 kHz
When using main clock: 4 to 64 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 240 kHz
Power supply voltage
3.2 V to 5.5 V (A/D converter: 3.5 V to 5.5 V) 3.2 V to 5.5 V (A/D converter: 3.5 V to 5.5 V)
Package
144-pin LQFP (20
×
20 mm) 208-pin LQFP (28
×
28 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850E/DG3 V850E/DJ3
Part No.
µPD70F3416 µPD70F3417 µPD70F3421 µPD70F3422 µPD70F3423
CPU name
V850E1 V850E1
CPU performance (Dhrystone)
34 MIPS (@ 16 MHz) 69 MIPS (@ 32 MHz)
Internal ROM
128 KB (ash) 256 KB (ash) 256 KB (ash) 384 KB (ash) 512 KB (ash)
Internal RAM
6 KB 12 KB 12 KB 16 KB 20 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal
48 (including one NMI) 75 (including one NMI)
External
5 (5)* (including one NMI) 8 (8)* (including one NMI)
Timer/counter
16-bit timer/event counter (TMP)
×
1 ch
16-bit timer/event counter (TMG)
×
2 ch
16-bit interval timer (TMZ)
×
4 ch
16-bit timer/event counter (TMP)
×
4 ch
16-bit timer/event counter (TMG)
×
3 ch
16-bit interval timer (TMZ)
×
6 ch
Watchdog timer
1 ch 1 ch
Serial interface
CSI
×
1 ch
I
2
C
×
1 ch
UART (LIN compatible)
×
2 ch
CSI
×
2 ch
I
2
C
×
2 ch
UART (LIN compatible)
×
2 ch
A/D converter
10 bits
×
8 ch 10 bits
×
12 ch
D/A converter
- -
DMA controller
-
4 ch
Ports I/O
72 98
Input
8 16
Debug control unit
-
Provided (RUN/break)
Other peripheral functions
Watch timer: 1 ch
Meter driver: 4 ch
ROM correction: 6 points, POC/clock monitor, SSCG
Sound generator
LCD controller/driver
CAN controller: 1 ch
Watch timer: 1 ch
Meter driver: 6 ch
ROM correction: 8 points, POC/clock monitor, SSCG
Voltage comparator
Sound generator
LCD controller/driver
CAN controller: 2 ch
Operating frequency
When using main clock: 4 to 16 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 240 kHz
When using main clock: 4 to 32 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 240 kHz
Power supply voltage
3.2 V to 5.5 V (A/D converter: 3.5 V to 5.5 V) 3.2 V to 5.5 V (A/D converter: 3.5 V to 5.5 V)
Package
100-pin LQFP (14
×
14 mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
62 63
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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